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From: Andrew Jones <ajones@ventanamicro.com>
To: Alexandre Ghiti <alexghiti@rivosinc.com>
Cc: Jonathan Corbet <corbet@lwn.net>,
	 Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	 Albert Ou <aou@eecs.berkeley.edu>,
	Conor Dooley <conor@kernel.org>, Rob Herring <robh@kernel.org>,
	 Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Andrea Parri <parri.andrea@gmail.com>,
	 Nathan Chancellor <nathan@kernel.org>,
	Peter Zijlstra <peterz@infradead.org>,
	 Ingo Molnar <mingo@redhat.com>, Will Deacon <will@kernel.org>,
	Waiman Long <longman@redhat.com>,
	 Boqun Feng <boqun.feng@gmail.com>, Arnd Bergmann <arnd@arndb.de>,
	 Leonardo Bras <leobras@redhat.com>, Guo Ren <guoren@kernel.org>,
	linux-doc@vger.kernel.org,  devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
	 linux-arch@vger.kernel.org
Subject: Re: [PATCH v4 01/13] riscv: Move cpufeature.h macros into their own header
Date: Wed, 31 Jul 2024 11:10:24 +0200	[thread overview]
Message-ID: <20240731-bdb567812a741c94a2c5d38a@orel> (raw)
In-Reply-To: <20240731072405.197046-2-alexghiti@rivosinc.com>

On Wed, Jul 31, 2024 at 09:23:53AM GMT, Alexandre Ghiti wrote:
> asm/cmpxchg.h will soon need riscv_has_extension_unlikely() macros and
> then needs to include asm/cpufeature.h which introduces a lot of header
> circular dependencies.

The includes of asm/cpufeature.h don't look well maintained. I don't think
it needs asm/errno.h and it should have linux/threads.h,
linux/percpu-defs.h, and linux/kconfig.h.

> 
> So move the riscv_has_extension_XXX() macros into their own header which
> prevents such circular dependencies by including a restricted number of
> headers.
> 
> Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>
> ---
>  arch/riscv/include/asm/cpufeature-macros.h | 66 ++++++++++++++++++++++
>  arch/riscv/include/asm/cpufeature.h        | 56 +-----------------
>  2 files changed, 67 insertions(+), 55 deletions(-)
>  create mode 100644 arch/riscv/include/asm/cpufeature-macros.h
> 
> diff --git a/arch/riscv/include/asm/cpufeature-macros.h b/arch/riscv/include/asm/cpufeature-macros.h
> new file mode 100644
> index 000000000000..c5f0bf75e026
> --- /dev/null
> +++ b/arch/riscv/include/asm/cpufeature-macros.h
> @@ -0,0 +1,66 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Copyright 2022-2024 Rivos, Inc
> + */
> +
> +#ifndef _ASM_CPUFEATURE_MACROS_H
> +#define _ASM_CPUFEATURE_MACROS_H
> +
> +#include <asm/hwcap.h>
> +#include <asm/alternative-macros.h>
> +
> +#define STANDARD_EXT		0
> +
> +bool __riscv_isa_extension_available(const unsigned long *isa_bitmap, unsigned int bit);
> +#define riscv_isa_extension_available(isa_bitmap, ext)	\
> +	__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_##ext)
> +
> +static __always_inline bool __riscv_has_extension_likely(const unsigned long vendor,
> +							 const unsigned long ext)
> +{
> +	asm goto(ALTERNATIVE("j	%l[l_no]", "nop", %[vendor], %[ext], 1)
> +	:
> +	: [vendor] "i" (vendor), [ext] "i" (ext)
> +	:
> +	: l_no);
> +
> +	return true;
> +l_no:
> +	return false;
> +}
> +
> +static __always_inline bool __riscv_has_extension_unlikely(const unsigned long vendor,
> +							   const unsigned long ext)
> +{
> +	asm goto(ALTERNATIVE("nop", "j	%l[l_yes]", %[vendor], %[ext], 1)
> +	:
> +	: [vendor] "i" (vendor), [ext] "i" (ext)
> +	:
> +	: l_yes);
> +
> +	return false;
> +l_yes:
> +	return true;
> +}
> +
> +static __always_inline bool riscv_has_extension_unlikely(const unsigned long ext)
> +{
> +	compiletime_assert(ext < RISCV_ISA_EXT_MAX, "ext must be < RISCV_ISA_EXT_MAX");
> +
> +	if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE))
> +		return __riscv_has_extension_unlikely(STANDARD_EXT, ext);
> +
> +	return __riscv_isa_extension_available(NULL, ext);
> +}
> +
> +static __always_inline bool riscv_has_extension_likely(const unsigned long ext)
> +{
> +	compiletime_assert(ext < RISCV_ISA_EXT_MAX, "ext must be < RISCV_ISA_EXT_MAX");
> +
> +	if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE))
> +		return __riscv_has_extension_likely(STANDARD_EXT, ext);
> +
> +	return __riscv_isa_extension_available(NULL, ext);
> +}
> +
> +#endif

nit: Add the /* _ASM_CPUFEATURE_MACROS_H */ here.

> diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/cpufeature.h
> index 45f9c1171a48..c991672bb401 100644
> --- a/arch/riscv/include/asm/cpufeature.h
> +++ b/arch/riscv/include/asm/cpufeature.h
> @@ -11,6 +11,7 @@
>  #include <asm/hwcap.h>
>  #include <asm/alternative-macros.h>

I think asm/alternative-macros.h can be dropped now.

>  #include <asm/errno.h>
> +#include <asm/cpufeature-macros.h>
>  
>  /*
>   * These are probed via a device_initcall(), via either the SBI or directly
> @@ -103,61 +104,6 @@ extern const size_t riscv_isa_ext_count;
>  extern bool riscv_isa_fallback;
>  
>  unsigned long riscv_isa_extension_base(const unsigned long *isa_bitmap);
> -
> -#define STANDARD_EXT		0
> -
> -bool __riscv_isa_extension_available(const unsigned long *isa_bitmap, unsigned int bit);
> -#define riscv_isa_extension_available(isa_bitmap, ext)	\
> -	__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_##ext)
> -
> -static __always_inline bool __riscv_has_extension_likely(const unsigned long vendor,
> -							 const unsigned long ext)
> -{
> -	asm goto(ALTERNATIVE("j	%l[l_no]", "nop", %[vendor], %[ext], 1)
> -	:
> -	: [vendor] "i" (vendor), [ext] "i" (ext)
> -	:
> -	: l_no);
> -
> -	return true;
> -l_no:
> -	return false;
> -}
> -
> -static __always_inline bool __riscv_has_extension_unlikely(const unsigned long vendor,
> -							   const unsigned long ext)
> -{
> -	asm goto(ALTERNATIVE("nop", "j	%l[l_yes]", %[vendor], %[ext], 1)
> -	:
> -	: [vendor] "i" (vendor), [ext] "i" (ext)
> -	:
> -	: l_yes);
> -
> -	return false;
> -l_yes:
> -	return true;
> -}
> -
> -static __always_inline bool riscv_has_extension_unlikely(const unsigned long ext)
> -{
> -	compiletime_assert(ext < RISCV_ISA_EXT_MAX, "ext must be < RISCV_ISA_EXT_MAX");
> -
> -	if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE))
> -		return __riscv_has_extension_unlikely(STANDARD_EXT, ext);
> -
> -	return __riscv_isa_extension_available(NULL, ext);
> -}
> -
> -static __always_inline bool riscv_has_extension_likely(const unsigned long ext)
> -{
> -	compiletime_assert(ext < RISCV_ISA_EXT_MAX, "ext must be < RISCV_ISA_EXT_MAX");
> -
> -	if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE))
> -		return __riscv_has_extension_likely(STANDARD_EXT, ext);
> -
> -	return __riscv_isa_extension_available(NULL, ext);
> -}
> -
>  static __always_inline bool riscv_cpu_has_extension_likely(int cpu, const unsigned long ext)
>  {
>  	compiletime_assert(ext < RISCV_ISA_EXT_MAX, "ext must be < RISCV_ISA_EXT_MAX");
> -- 
> 2.39.2
> 
>

Otherwise,

Reviewed-by: Andrew Jones <ajones@ventanamicro.com>

Thanks,
drew

  reply	other threads:[~2024-07-31  9:10 UTC|newest]

Thread overview: 47+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-07-31  7:23 [PATCH v4 00/13] Zacas/Zabha support and qspinlocks Alexandre Ghiti
2024-07-31  7:23 ` [PATCH v4 01/13] riscv: Move cpufeature.h macros into their own header Alexandre Ghiti
2024-07-31  9:10   ` Andrew Jones [this message]
2024-07-31  7:23 ` [PATCH v4 02/13] riscv: Do not fail to build on byte/halfword operations with Zawrs Alexandre Ghiti
2024-07-31 14:10   ` Andrew Jones
2024-07-31 15:52     ` Alexandre Ghiti
2024-07-31 16:14       ` Andrew Jones
2024-08-01  6:30         ` Alexandre Ghiti
2024-07-31 16:27   ` Waiman Long
2024-07-31 21:51     ` Guo Ren
2024-07-31  7:23 ` [PATCH v4 03/13] riscv: Implement cmpxchg32/64() using Zacas Alexandre Ghiti
2024-07-31  9:21   ` Andrew Jones
2024-07-31  7:23 ` [PATCH v4 04/13] dt-bindings: riscv: Add Zabha ISA extension description Alexandre Ghiti
2024-08-01 14:53   ` Conor Dooley
2024-07-31  7:23 ` [PATCH v4 05/13] riscv: Implement cmpxchg8/16() using Zabha Alexandre Ghiti
2024-07-31  9:27   ` Andrew Jones
2024-07-31  7:23 ` [PATCH v4 06/13] riscv: Improve zacas fully-ordered cmpxchg() Alexandre Ghiti
2024-07-31  9:59   ` Andrew Jones
2024-07-31 10:33     ` Andrea Parri
2024-08-01  6:15     ` Alexandre Ghiti
2024-07-31  7:23 ` [PATCH v4 07/13] riscv: Implement arch_cmpxchg128() using Zacas Alexandre Ghiti
2024-07-31 15:41   ` Andrew Jones
2024-07-31  7:24 ` [PATCH v4 08/13] riscv: Implement xchg8/16() using Zabha Alexandre Ghiti
2024-07-31 12:20   ` Andrew Jones
2024-07-31  7:24 ` [PATCH v4 09/13] asm-generic: ticket-lock: Reuse arch_spinlock_t of qspinlock Alexandre Ghiti
2024-07-31  7:24 ` [PATCH v4 10/13] asm-generic: ticket-lock: Add separate ticket-lock.h Alexandre Ghiti
2024-07-31  7:24 ` [PATCH v4 11/13] riscv: Add ISA extension parsing for Ziccrse Alexandre Ghiti
2024-07-31  7:24 ` [PATCH v4 12/13] dt-bindings: riscv: Add Ziccrse ISA extension description Alexandre Ghiti
2024-08-01 14:44   ` Conor Dooley
2024-08-02  8:14     ` Alexandre Ghiti
2024-08-02 14:46       ` Conor Dooley
2024-07-31  7:24 ` [PATCH v4 13/13] riscv: Add qspinlock support Alexandre Ghiti
2024-07-31 15:29   ` Andrew Jones
2024-08-01  6:53     ` Alexandre Ghiti
2024-08-01  7:48       ` Andrew Jones
2024-08-02  8:31         ` Alexandre Ghiti
2024-08-15 13:27       ` Alexandre Ghiti
2024-08-15 13:34         ` Andrew Jones
2024-08-17  5:08         ` Guo Ren
2024-08-21 12:18           ` Andrew Jones
2024-08-27  8:02             ` Alexandre Ghiti
2024-08-27  8:03           ` Alexandre Ghiti
2024-08-01  8:43     ` Alexandre Ghiti
2024-08-01 10:15       ` Andrew Jones
2024-08-02  8:58         ` Alexandre Ghiti
2024-08-01  9:48     ` Andrea Parri
2024-08-01 14:15 ` [PATCH v4 00/13] Zacas/Zabha support and qspinlocks Peter Zijlstra

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