devicetree.vger.kernel.org archive mirror
 help / color / mirror / Atom feed
From: matthew.gerlach@linux.intel.com
To: lpieralisi@kernel.org, kw@linux.com, robh@kernel.org,
	bhelgaas@google.com, krzk+dt@kernel.org, conor+dt@kernel.org,
	dinguyen@kernel.org, joyce.ooi@intel.com,
	linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org
Cc: Matthew Gerlach <matthew.gerlach@linux.intel.com>
Subject: [PATCH 0/7] Add PCIe Root Port support for Agilex family of chips
Date: Wed, 31 Jul 2024 09:39:39 -0500	[thread overview]
Message-ID: <20240731143946.3478057-1-matthew.gerlach@linux.intel.com> (raw)

From: Matthew Gerlach <matthew.gerlach@linux.intel.com>

This patch set adds PCIe Root Port support for the Agilex family of FPGA chips.
Patches 1 and 2 have been reviewed previously and individually on the mailing
list and are included here with their revision history and Reviewed-by: tags
for convenience and completeness.

Patch 1: 
  Convert text device tree binding for Altera Root Port PCIe controller to YAML.

Patch 2:
  Convert text device tree binding for Altera PCIe MSI controller to YAML.

Patch 3:
  Add new compatible strings for the three variants of the Agilex PCIe controller IP.

Patch 4:
  Add a label to the soc@0 device tree node to be used by patch 5.

Patch 5:
  Add base dtsi for PCIe Root Port support of the Agilex family of chips.

Patch 6:
  Add dts enabling PCIe Root Port support on an Agilex F-series Development Kit.

Patch 7:
  Update Altera PCIe controller driver to support the Agilex family of chips.

D M, Sharath Kumar (1):
  pci: controller: pcie-altera: Add support for Agilex

Matthew Gerlach (6):
  dt-bindings: PCI: altera: Convert to YAML
  dt-bindings: PCI: altera: msi: Convert to YAML
  dt-bindings: PCI: altera: Add binding for Agilex
  arm64: dts: agilex: add soc0 label
  arm64: dts: agilex: add dtsi for PCIe Root Port
  arm64: dts: agilex: add dts enabling PCIe Root Port

 .../bindings/pci/altera-pcie-msi.txt          |  27 --
 .../devicetree/bindings/pci/altera-pcie.txt   |  50 ----
 .../bindings/pci/altr,msi-controller.yaml     |  65 +++++
 .../bindings/pci/altr,pcie-root-port.yaml     | 123 +++++++++
 MAINTAINERS                                   |   4 +-
 arch/arm64/boot/dts/intel/Makefile            |   1 +
 arch/arm64/boot/dts/intel/socfpga_agilex.dtsi |   2 +-
 .../socfpga_agilex7f_socdk_pcie_root_port.dts |  16 ++
 .../intel/socfpga_agilex_pcie_root_port.dtsi  |  55 ++++
 drivers/pci/controller/pcie-altera.c          | 260 ++++++++++++++++--
 10 files changed, 507 insertions(+), 96 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/pci/altera-pcie-msi.txt
 delete mode 100644 Documentation/devicetree/bindings/pci/altera-pcie.txt
 create mode 100644 Documentation/devicetree/bindings/pci/altr,msi-controller.yaml
 create mode 100644 Documentation/devicetree/bindings/pci/altr,pcie-root-port.yaml
 create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex7f_socdk_pcie_root_port.dts
 create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex_pcie_root_port.dtsi

-- 
2.34.1


             reply	other threads:[~2024-07-31 14:41 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-07-31 14:39 matthew.gerlach [this message]
2024-07-31 14:39 ` [PATCH 1/7] dt-bindings: PCI: altera: Convert to YAML matthew.gerlach
2024-07-31 14:39 ` [PATCH 2/7] dt-bindings: PCI: altera: msi: " matthew.gerlach
2024-07-31 14:39 ` [PATCH 3/7] dt-bindings: PCI: altera: Add binding for Agilex matthew.gerlach
2024-08-06 17:01   ` Rob Herring (Arm)
2024-07-31 14:39 ` [PATCH 4/7] arm64: dts: agilex: add soc0 label matthew.gerlach
2024-07-31 14:39 ` [PATCH 5/7] arm64: dts: agilex: add dtsi for PCIe Root Port matthew.gerlach
2024-08-07 23:03   ` matthew.gerlach
2024-07-31 14:39 ` [PATCH 6/7] arm64: dts: agilex: add dts enabling " matthew.gerlach
2024-07-31 14:39 ` [PATCH 7/7] pci: controller: pcie-altera: Add support for Agilex matthew.gerlach
2024-07-31 20:23   ` Bjorn Helgaas
2024-08-02  0:07     ` matthew.gerlach
2024-08-01 15:29 ` [PATCH 0/7] Add PCIe Root Port support for Agilex family of chips Rob Herring (Arm)

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20240731143946.3478057-1-matthew.gerlach@linux.intel.com \
    --to=matthew.gerlach@linux.intel.com \
    --cc=bhelgaas@google.com \
    --cc=conor+dt@kernel.org \
    --cc=devicetree@vger.kernel.org \
    --cc=dinguyen@kernel.org \
    --cc=joyce.ooi@intel.com \
    --cc=krzk+dt@kernel.org \
    --cc=kw@linux.com \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-pci@vger.kernel.org \
    --cc=lpieralisi@kernel.org \
    --cc=robh@kernel.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).