From: Drew Fustini <drew@pdp7.com>
To: Emil Renner Berthing <emil.renner.berthing@canonical.com>,
Thomas Bonnefille <thomas.bonnefille@bootlin.com>,
Kanak Shilledar <kanakshilledar@gmail.com>,
Jisheng Zhang <jszhang@kernel.org>, Guo Ren <guoren@kernel.org>,
Fu Wei <wefu@redhat.com>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>
Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, Drew Fustini <drew@pdp7.com>,
Drew Fustini <dfustini@tenstorrent.com>
Subject: [PATCH 2/6] riscv: dts: thead: change TH1520 uart nodes to use clock controller
Date: Thu, 01 Aug 2024 11:38:06 -0700 [thread overview]
Message-ID: <20240801-th1520-clk-dts-v1-2-71077a0614b8@pdp7.com> (raw)
In-Reply-To: <20240801-th1520-clk-dts-v1-0-71077a0614b8@pdp7.com>
From: Drew Fustini <dfustini@tenstorrent.com>
Change the clock property in TH1520 uart nodes to a clock provided by
AP_SUBSYS clock controller.
Link: https://git.beagleboard.org/beaglev-ahead/beaglev-ahead/-/tree/main/docs
Signed-off-by: Drew Fustini <dfustini@tenstorrent.com>
---
arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts | 4 ----
.../boot/dts/thead/th1520-lichee-module-4a.dtsi | 4 ----
arch/riscv/boot/dts/thead/th1520.dtsi | 24 +++++++++++-----------
3 files changed, 12 insertions(+), 20 deletions(-)
diff --git a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts
index b4d2e1d69bdb..90585883b059 100644
--- a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts
+++ b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts
@@ -57,10 +57,6 @@ &spi_clk {
clock-frequency = <396000000>;
};
-&uart_sclk {
- clock-frequency = <100000000>;
-};
-
&dmac0 {
status = "okay";
};
diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi
index 6939bd36560c..1c5c7075ae17 100644
--- a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi
+++ b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi
@@ -37,10 +37,6 @@ &spi_clk {
clock-frequency = <396000000>;
};
-&uart_sclk {
- clock-frequency = <100000000>;
-};
-
&dmac0 {
status = "okay";
};
diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi
index 25ef5ee729e6..a543be8d6e37 100644
--- a/arch/riscv/boot/dts/thead/th1520.dtsi
+++ b/arch/riscv/boot/dts/thead/th1520.dtsi
@@ -228,12 +228,6 @@ spi_clk: spi-clock {
#clock-cells = <0>;
};
- uart_sclk: uart-sclk-clock {
- compatible = "fixed-clock";
- clock-output-names = "uart_sclk";
- #clock-cells = <0>;
- };
-
sdhci_clk: sdhci-clock {
compatible = "fixed-clock";
clock-frequency = <198000000>;
@@ -285,7 +279,8 @@ uart0: serial@ffe7014000 {
compatible = "snps,dw-apb-uart";
reg = <0xff 0xe7014000 0x0 0x100>;
interrupts = <36 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&uart_sclk>;
+ clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART0_PCLK>;
+ clock-names = "baudclk", "apb_pclk";
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
@@ -322,7 +317,8 @@ uart1: serial@ffe7f00000 {
compatible = "snps,dw-apb-uart";
reg = <0xff 0xe7f00000 0x0 0x100>;
interrupts = <37 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&uart_sclk>;
+ clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART1_PCLK>;
+ clock-names = "baudclk", "apb_pclk";
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
@@ -332,7 +328,8 @@ uart3: serial@ffe7f04000 {
compatible = "snps,dw-apb-uart";
reg = <0xff 0xe7f04000 0x0 0x100>;
interrupts = <39 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&uart_sclk>;
+ clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART3_PCLK>;
+ clock-names = "baudclk", "apb_pclk";
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
@@ -414,7 +411,8 @@ uart2: serial@ffec010000 {
compatible = "snps,dw-apb-uart";
reg = <0xff 0xec010000 0x0 0x4000>;
interrupts = <38 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&uart_sclk>;
+ clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART2_PCLK>;
+ clock-names = "baudclk", "apb_pclk";
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
@@ -483,7 +481,8 @@ uart4: serial@fff7f08000 {
compatible = "snps,dw-apb-uart";
reg = <0xff 0xf7f08000 0x0 0x4000>;
interrupts = <40 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&uart_sclk>;
+ clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART4_PCLK>;
+ clock-names = "baudclk", "apb_pclk";
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
@@ -493,7 +492,8 @@ uart5: serial@fff7f0c000 {
compatible = "snps,dw-apb-uart";
reg = <0xff 0xf7f0c000 0x0 0x4000>;
interrupts = <41 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&uart_sclk>;
+ clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART5_PCLK>;
+ clock-names = "baudclk", "apb_pclk";
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
--
2.34.1
next prev parent reply other threads:[~2024-08-01 18:38 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-08-01 18:38 [PATCH 0/6] riscv: dts: thead: Enable TH1520 AP_SUBSYS clock controller Drew Fustini
2024-08-01 18:38 ` [PATCH 1/6] riscv: dts: thead: Add " Drew Fustini
2024-08-01 18:38 ` Drew Fustini [this message]
2024-08-01 18:38 ` [PATCH 3/6] riscv: dts: thead: change TH1520 mmc nodes to use " Drew Fustini
2024-08-01 18:38 ` [PATCH 4/6] riscv: dts: thead: update TH1520 dma and timer " Drew Fustini
2024-08-01 18:38 ` [PATCH 5/6] riscv: dts: thead: add clock to TH1520 gpio nodes Drew Fustini
2024-08-01 18:38 ` [PATCH 6/6] riscv: dts: thead: change TH1520 SPI node to use clock controller Drew Fustini
2024-08-08 18:22 ` [PATCH 0/6] riscv: dts: thead: Enable TH1520 AP_SUBSYS " Drew Fustini
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