* [PATCH 1/6] riscv: dts: thead: Add TH1520 AP_SUBSYS clock controller
2024-08-01 18:38 [PATCH 0/6] riscv: dts: thead: Enable TH1520 AP_SUBSYS clock controller Drew Fustini
@ 2024-08-01 18:38 ` Drew Fustini
2024-08-01 18:38 ` [PATCH 2/6] riscv: dts: thead: change TH1520 uart nodes to use " Drew Fustini
` (5 subsequent siblings)
6 siblings, 0 replies; 8+ messages in thread
From: Drew Fustini @ 2024-08-01 18:38 UTC (permalink / raw)
To: Emil Renner Berthing, Thomas Bonnefille, Kanak Shilledar,
Jisheng Zhang, Guo Ren, Fu Wei, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou
Cc: linux-riscv, devicetree, linux-kernel, Drew Fustini, Drew Fustini
From: Drew Fustini <dfustini@tenstorrent.com>
Add node for the AP_SUBSYS clock controller on the T-Head TH1520 SoC.
Link: https://openbeagle.org/beaglev-ahead/beaglev-ahead/-/blob/main/docs/TH1520%20System%20User%20Manual.pdf
Link: https://git.beagleboard.org/beaglev-ahead/beaglev-ahead/-/tree/main/docs
Signed-off-by: Drew Fustini <dfustini@tenstorrent.com>
---
arch/riscv/boot/dts/thead/th1520.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi
index aa703da30fc3..25ef5ee729e6 100644
--- a/arch/riscv/boot/dts/thead/th1520.dtsi
+++ b/arch/riscv/boot/dts/thead/th1520.dtsi
@@ -5,6 +5,7 @@
*/
#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/clock/thead,th1520-clk-ap.h>
/ {
compatible = "thead,th1520";
@@ -419,6 +420,13 @@ uart2: serial@ffec010000 {
status = "disabled";
};
+ clk: clock-controller@ffef010000 {
+ compatible = "thead,th1520-clk-ap";
+ reg = <0xff 0xef010000 0x0 0x1000>;
+ clocks = <&osc>;
+ #clock-cells = <1>;
+ };
+
dmac0: dma-controller@ffefc00000 {
compatible = "snps,axi-dma-1.01a";
reg = <0xff 0xefc00000 0x0 0x1000>;
--
2.34.1
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH 2/6] riscv: dts: thead: change TH1520 uart nodes to use clock controller
2024-08-01 18:38 [PATCH 0/6] riscv: dts: thead: Enable TH1520 AP_SUBSYS clock controller Drew Fustini
2024-08-01 18:38 ` [PATCH 1/6] riscv: dts: thead: Add " Drew Fustini
@ 2024-08-01 18:38 ` Drew Fustini
2024-08-01 18:38 ` [PATCH 3/6] riscv: dts: thead: change TH1520 mmc " Drew Fustini
` (4 subsequent siblings)
6 siblings, 0 replies; 8+ messages in thread
From: Drew Fustini @ 2024-08-01 18:38 UTC (permalink / raw)
To: Emil Renner Berthing, Thomas Bonnefille, Kanak Shilledar,
Jisheng Zhang, Guo Ren, Fu Wei, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou
Cc: linux-riscv, devicetree, linux-kernel, Drew Fustini, Drew Fustini
From: Drew Fustini <dfustini@tenstorrent.com>
Change the clock property in TH1520 uart nodes to a clock provided by
AP_SUBSYS clock controller.
Link: https://git.beagleboard.org/beaglev-ahead/beaglev-ahead/-/tree/main/docs
Signed-off-by: Drew Fustini <dfustini@tenstorrent.com>
---
arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts | 4 ----
.../boot/dts/thead/th1520-lichee-module-4a.dtsi | 4 ----
arch/riscv/boot/dts/thead/th1520.dtsi | 24 +++++++++++-----------
3 files changed, 12 insertions(+), 20 deletions(-)
diff --git a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts
index b4d2e1d69bdb..90585883b059 100644
--- a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts
+++ b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts
@@ -57,10 +57,6 @@ &spi_clk {
clock-frequency = <396000000>;
};
-&uart_sclk {
- clock-frequency = <100000000>;
-};
-
&dmac0 {
status = "okay";
};
diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi
index 6939bd36560c..1c5c7075ae17 100644
--- a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi
+++ b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi
@@ -37,10 +37,6 @@ &spi_clk {
clock-frequency = <396000000>;
};
-&uart_sclk {
- clock-frequency = <100000000>;
-};
-
&dmac0 {
status = "okay";
};
diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi
index 25ef5ee729e6..a543be8d6e37 100644
--- a/arch/riscv/boot/dts/thead/th1520.dtsi
+++ b/arch/riscv/boot/dts/thead/th1520.dtsi
@@ -228,12 +228,6 @@ spi_clk: spi-clock {
#clock-cells = <0>;
};
- uart_sclk: uart-sclk-clock {
- compatible = "fixed-clock";
- clock-output-names = "uart_sclk";
- #clock-cells = <0>;
- };
-
sdhci_clk: sdhci-clock {
compatible = "fixed-clock";
clock-frequency = <198000000>;
@@ -285,7 +279,8 @@ uart0: serial@ffe7014000 {
compatible = "snps,dw-apb-uart";
reg = <0xff 0xe7014000 0x0 0x100>;
interrupts = <36 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&uart_sclk>;
+ clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART0_PCLK>;
+ clock-names = "baudclk", "apb_pclk";
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
@@ -322,7 +317,8 @@ uart1: serial@ffe7f00000 {
compatible = "snps,dw-apb-uart";
reg = <0xff 0xe7f00000 0x0 0x100>;
interrupts = <37 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&uart_sclk>;
+ clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART1_PCLK>;
+ clock-names = "baudclk", "apb_pclk";
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
@@ -332,7 +328,8 @@ uart3: serial@ffe7f04000 {
compatible = "snps,dw-apb-uart";
reg = <0xff 0xe7f04000 0x0 0x100>;
interrupts = <39 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&uart_sclk>;
+ clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART3_PCLK>;
+ clock-names = "baudclk", "apb_pclk";
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
@@ -414,7 +411,8 @@ uart2: serial@ffec010000 {
compatible = "snps,dw-apb-uart";
reg = <0xff 0xec010000 0x0 0x4000>;
interrupts = <38 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&uart_sclk>;
+ clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART2_PCLK>;
+ clock-names = "baudclk", "apb_pclk";
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
@@ -483,7 +481,8 @@ uart4: serial@fff7f08000 {
compatible = "snps,dw-apb-uart";
reg = <0xff 0xf7f08000 0x0 0x4000>;
interrupts = <40 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&uart_sclk>;
+ clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART4_PCLK>;
+ clock-names = "baudclk", "apb_pclk";
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
@@ -493,7 +492,8 @@ uart5: serial@fff7f0c000 {
compatible = "snps,dw-apb-uart";
reg = <0xff 0xf7f0c000 0x0 0x4000>;
interrupts = <41 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&uart_sclk>;
+ clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART5_PCLK>;
+ clock-names = "baudclk", "apb_pclk";
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
--
2.34.1
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH 3/6] riscv: dts: thead: change TH1520 mmc nodes to use clock controller
2024-08-01 18:38 [PATCH 0/6] riscv: dts: thead: Enable TH1520 AP_SUBSYS clock controller Drew Fustini
2024-08-01 18:38 ` [PATCH 1/6] riscv: dts: thead: Add " Drew Fustini
2024-08-01 18:38 ` [PATCH 2/6] riscv: dts: thead: change TH1520 uart nodes to use " Drew Fustini
@ 2024-08-01 18:38 ` Drew Fustini
2024-08-01 18:38 ` [PATCH 4/6] riscv: dts: thead: update TH1520 dma and timer " Drew Fustini
` (3 subsequent siblings)
6 siblings, 0 replies; 8+ messages in thread
From: Drew Fustini @ 2024-08-01 18:38 UTC (permalink / raw)
To: Emil Renner Berthing, Thomas Bonnefille, Kanak Shilledar,
Jisheng Zhang, Guo Ren, Fu Wei, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou
Cc: linux-riscv, devicetree, linux-kernel, Drew Fustini, Drew Fustini
From: Drew Fustini <dfustini@tenstorrent.com>
Change the clock property in the TH1520 mmc controller nodes to a clock
provided by AP_SYS clock controller.
Remove sdhci fixed clock reference from BeagleV Ahead and LPI4a dts.
Link: https://git.beagleboard.org/beaglev-ahead/beaglev-ahead/-/tree/main/docs
Signed-off-by: Drew Fustini <dfustini@tenstorrent.com>
---
arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts | 4 ----
arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi | 4 ----
arch/riscv/boot/dts/thead/th1520.dtsi | 13 +++----------
3 files changed, 3 insertions(+), 18 deletions(-)
diff --git a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts
index 90585883b059..5169a718f79c 100644
--- a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts
+++ b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts
@@ -49,10 +49,6 @@ &apb_clk {
clock-frequency = <62500000>;
};
-&sdhci_clk {
- clock-frequency = <198000000>;
-};
-
&spi_clk {
clock-frequency = <396000000>;
};
diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi
index 1c5c7075ae17..be982a3ac18c 100644
--- a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi
+++ b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi
@@ -29,10 +29,6 @@ &apb_clk {
clock-frequency = <62500000>;
};
-&sdhci_clk {
- clock-frequency = <198000000>;
-};
-
&spi_clk {
clock-frequency = <396000000>;
};
diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi
index a543be8d6e37..f3b2f8236096 100644
--- a/arch/riscv/boot/dts/thead/th1520.dtsi
+++ b/arch/riscv/boot/dts/thead/th1520.dtsi
@@ -228,13 +228,6 @@ spi_clk: spi-clock {
#clock-cells = <0>;
};
- sdhci_clk: sdhci-clock {
- compatible = "fixed-clock";
- clock-frequency = <198000000>;
- clock-output-names = "sdhci_clk";
- #clock-cells = <0>;
- };
-
soc {
compatible = "simple-bus";
interrupt-parent = <&plic>;
@@ -290,7 +283,7 @@ emmc: mmc@ffe7080000 {
compatible = "thead,th1520-dwcmshc";
reg = <0xff 0xe7080000 0x0 0x10000>;
interrupts = <62 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&sdhci_clk>;
+ clocks = <&clk CLK_EMMC_SDIO>;
clock-names = "core";
status = "disabled";
};
@@ -299,7 +292,7 @@ sdio0: mmc@ffe7090000 {
compatible = "thead,th1520-dwcmshc";
reg = <0xff 0xe7090000 0x0 0x10000>;
interrupts = <64 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&sdhci_clk>;
+ clocks = <&clk CLK_EMMC_SDIO>;
clock-names = "core";
status = "disabled";
};
@@ -308,7 +301,7 @@ sdio1: mmc@ffe70a0000 {
compatible = "thead,th1520-dwcmshc";
reg = <0xff 0xe70a0000 0x0 0x10000>;
interrupts = <71 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&sdhci_clk>;
+ clocks = <&clk CLK_EMMC_SDIO>;
clock-names = "core";
status = "disabled";
};
--
2.34.1
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH 4/6] riscv: dts: thead: update TH1520 dma and timer nodes to use clock controller
2024-08-01 18:38 [PATCH 0/6] riscv: dts: thead: Enable TH1520 AP_SUBSYS clock controller Drew Fustini
` (2 preceding siblings ...)
2024-08-01 18:38 ` [PATCH 3/6] riscv: dts: thead: change TH1520 mmc " Drew Fustini
@ 2024-08-01 18:38 ` Drew Fustini
2024-08-01 18:38 ` [PATCH 5/6] riscv: dts: thead: add clock to TH1520 gpio nodes Drew Fustini
` (2 subsequent siblings)
6 siblings, 0 replies; 8+ messages in thread
From: Drew Fustini @ 2024-08-01 18:38 UTC (permalink / raw)
To: Emil Renner Berthing, Thomas Bonnefille, Kanak Shilledar,
Jisheng Zhang, Guo Ren, Fu Wei, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou
Cc: linux-riscv, devicetree, linux-kernel, Drew Fustini, Drew Fustini
From: Drew Fustini <dfustini@tenstorrent.com>
Change the dma-controller and timer nodes to use the APB clock provided
by the AP_SUBSYS clock controller.
Remove apb_clk reference from BeagleV Ahead and LPI4a dts.
Link: https://git.beagleboard.org/beaglev-ahead/beaglev-ahead/-/tree/main/docs
Signed-off-by: Drew Fustini <dfustini@tenstorrent.com>
---
arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts | 4 ----
.../boot/dts/thead/th1520-lichee-module-4a.dtsi | 4 ----
arch/riscv/boot/dts/thead/th1520.dtsi | 24 ++++++++--------------
3 files changed, 9 insertions(+), 23 deletions(-)
diff --git a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts
index 5169a718f79c..425f07d73b32 100644
--- a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts
+++ b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts
@@ -45,10 +45,6 @@ &osc_32k {
clock-frequency = <32768>;
};
-&apb_clk {
- clock-frequency = <62500000>;
-};
-
&spi_clk {
clock-frequency = <396000000>;
};
diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi
index be982a3ac18c..077dbbe4abb6 100644
--- a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi
+++ b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi
@@ -25,10 +25,6 @@ &osc_32k {
clock-frequency = <32768>;
};
-&apb_clk {
- clock-frequency = <62500000>;
-};
-
&spi_clk {
clock-frequency = <396000000>;
};
diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi
index f3b2f8236096..6ea5cabbcf60 100644
--- a/arch/riscv/boot/dts/thead/th1520.dtsi
+++ b/arch/riscv/boot/dts/thead/th1520.dtsi
@@ -216,12 +216,6 @@ osc_32k: 32k-oscillator {
#clock-cells = <0>;
};
- apb_clk: apb-clk-clock {
- compatible = "fixed-clock";
- clock-output-names = "apb_clk";
- #clock-cells = <0>;
- };
-
spi_clk: spi-clock {
compatible = "fixed-clock";
clock-output-names = "spi_clk";
@@ -422,7 +416,7 @@ dmac0: dma-controller@ffefc00000 {
compatible = "snps,axi-dma-1.01a";
reg = <0xff 0xefc00000 0x0 0x1000>;
interrupts = <27 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&apb_clk>, <&apb_clk>;
+ clocks = <&clk CLK_PERI_APB_PCLK>, <&clk CLK_PERI_APB_PCLK>;
clock-names = "core-clk", "cfgr-clk";
#dma-cells = <1>;
dma-channels = <4>;
@@ -437,7 +431,7 @@ dmac0: dma-controller@ffefc00000 {
timer0: timer@ffefc32000 {
compatible = "snps,dw-apb-timer";
reg = <0xff 0xefc32000 0x0 0x14>;
- clocks = <&apb_clk>;
+ clocks = <&clk CLK_PERI_APB_PCLK>;
clock-names = "timer";
interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
@@ -446,7 +440,7 @@ timer0: timer@ffefc32000 {
timer1: timer@ffefc32014 {
compatible = "snps,dw-apb-timer";
reg = <0xff 0xefc32014 0x0 0x14>;
- clocks = <&apb_clk>;
+ clocks = <&clk CLK_PERI_APB_PCLK>;
clock-names = "timer";
interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
@@ -455,7 +449,7 @@ timer1: timer@ffefc32014 {
timer2: timer@ffefc32028 {
compatible = "snps,dw-apb-timer";
reg = <0xff 0xefc32028 0x0 0x14>;
- clocks = <&apb_clk>;
+ clocks = <&clk CLK_PERI_APB_PCLK>;
clock-names = "timer";
interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
@@ -464,7 +458,7 @@ timer2: timer@ffefc32028 {
timer3: timer@ffefc3203c {
compatible = "snps,dw-apb-timer";
reg = <0xff 0xefc3203c 0x0 0x14>;
- clocks = <&apb_clk>;
+ clocks = <&clk CLK_PERI_APB_PCLK>;
clock-names = "timer";
interrupts = <19 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
@@ -495,7 +489,7 @@ uart5: serial@fff7f0c000 {
timer4: timer@ffffc33000 {
compatible = "snps,dw-apb-timer";
reg = <0xff 0xffc33000 0x0 0x14>;
- clocks = <&apb_clk>;
+ clocks = <&clk CLK_PERI_APB_PCLK>;
clock-names = "timer";
interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
@@ -504,7 +498,7 @@ timer4: timer@ffffc33000 {
timer5: timer@ffffc33014 {
compatible = "snps,dw-apb-timer";
reg = <0xff 0xffc33014 0x0 0x14>;
- clocks = <&apb_clk>;
+ clocks = <&clk CLK_PERI_APB_PCLK>;
clock-names = "timer";
interrupts = <21 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
@@ -513,7 +507,7 @@ timer5: timer@ffffc33014 {
timer6: timer@ffffc33028 {
compatible = "snps,dw-apb-timer";
reg = <0xff 0xffc33028 0x0 0x14>;
- clocks = <&apb_clk>;
+ clocks = <&clk CLK_PERI_APB_PCLK>;
clock-names = "timer";
interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
@@ -522,7 +516,7 @@ timer6: timer@ffffc33028 {
timer7: timer@ffffc3303c {
compatible = "snps,dw-apb-timer";
reg = <0xff 0xffc3303c 0x0 0x14>;
- clocks = <&apb_clk>;
+ clocks = <&clk CLK_PERI_APB_PCLK>;
clock-names = "timer";
interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
--
2.34.1
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH 5/6] riscv: dts: thead: add clock to TH1520 gpio nodes
2024-08-01 18:38 [PATCH 0/6] riscv: dts: thead: Enable TH1520 AP_SUBSYS clock controller Drew Fustini
` (3 preceding siblings ...)
2024-08-01 18:38 ` [PATCH 4/6] riscv: dts: thead: update TH1520 dma and timer " Drew Fustini
@ 2024-08-01 18:38 ` Drew Fustini
2024-08-01 18:38 ` [PATCH 6/6] riscv: dts: thead: change TH1520 SPI node to use clock controller Drew Fustini
2024-08-08 18:22 ` [PATCH 0/6] riscv: dts: thead: Enable TH1520 AP_SUBSYS " Drew Fustini
6 siblings, 0 replies; 8+ messages in thread
From: Drew Fustini @ 2024-08-01 18:38 UTC (permalink / raw)
To: Emil Renner Berthing, Thomas Bonnefille, Kanak Shilledar,
Jisheng Zhang, Guo Ren, Fu Wei, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou
Cc: linux-riscv, devicetree, linux-kernel, Drew Fustini, Drew Fustini
From: Drew Fustini <dfustini@tenstorrent.com>
Add clock property to TH1520 gpio controller nodes. These clock gates
refer to corresponding enable bits in the peripheral clock gate control
register. Refer to register PERI_CLK_CFG in section 4.4.2.2.52 of the
TH1520 System User Manual.
Link: https://git.beagleboard.org/beaglev-ahead/beaglev-ahead/-/tree/main/docs
Signed-off-by: Drew Fustini <dfustini@tenstorrent.com>
---
arch/riscv/boot/dts/thead/th1520.dtsi | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi
index 6ea5cabbcf60..5f4f94ca9cc7 100644
--- a/arch/riscv/boot/dts/thead/th1520.dtsi
+++ b/arch/riscv/boot/dts/thead/th1520.dtsi
@@ -327,6 +327,7 @@ gpio2: gpio@ffe7f34000 {
reg = <0xff 0xe7f34000 0x0 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
+ clocks = <&clk CLK_GPIO2>;
portc: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
@@ -345,6 +346,7 @@ gpio3: gpio@ffe7f38000 {
reg = <0xff 0xe7f38000 0x0 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
+ clocks = <&clk CLK_GPIO3>;
portd: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
@@ -363,6 +365,7 @@ gpio0: gpio@ffec005000 {
reg = <0xff 0xec005000 0x0 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
+ clocks = <&clk CLK_GPIO0>;
porta: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
@@ -381,6 +384,7 @@ gpio1: gpio@ffec006000 {
reg = <0xff 0xec006000 0x0 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
+ clocks = <&clk CLK_GPIO1>;
portb: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
--
2.34.1
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH 6/6] riscv: dts: thead: change TH1520 SPI node to use clock controller
2024-08-01 18:38 [PATCH 0/6] riscv: dts: thead: Enable TH1520 AP_SUBSYS clock controller Drew Fustini
` (4 preceding siblings ...)
2024-08-01 18:38 ` [PATCH 5/6] riscv: dts: thead: add clock to TH1520 gpio nodes Drew Fustini
@ 2024-08-01 18:38 ` Drew Fustini
2024-08-08 18:22 ` [PATCH 0/6] riscv: dts: thead: Enable TH1520 AP_SUBSYS " Drew Fustini
6 siblings, 0 replies; 8+ messages in thread
From: Drew Fustini @ 2024-08-01 18:38 UTC (permalink / raw)
To: Emil Renner Berthing, Thomas Bonnefille, Kanak Shilledar,
Jisheng Zhang, Guo Ren, Fu Wei, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou
Cc: linux-riscv, devicetree, linux-kernel, Drew Fustini, Drew Fustini
From: Drew Fustini <dfustini@tenstorrent.com>
Change the clock property in the TH1520 SPI controller node to a clock
provided by AP_SYS clock controller.
Remove spi_clk fixed clock reference from BeagleV Ahead and LPI4a dts.
Link: https://git.beagleboard.org/beaglev-ahead/beaglev-ahead/-/tree/main/docs
Signed-off-by: Drew Fustini <dfustini@tenstorrent.com>
---
arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts | 4 ----
arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi | 4 ----
arch/riscv/boot/dts/thead/th1520.dtsi | 8 +-------
3 files changed, 1 insertion(+), 15 deletions(-)
diff --git a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts
index 425f07d73b32..497d961456f3 100644
--- a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts
+++ b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts
@@ -45,10 +45,6 @@ &osc_32k {
clock-frequency = <32768>;
};
-&spi_clk {
- clock-frequency = <396000000>;
-};
-
&dmac0 {
status = "okay";
};
diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi
index 077dbbe4abb6..78977bdbbe3d 100644
--- a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi
+++ b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi
@@ -25,10 +25,6 @@ &osc_32k {
clock-frequency = <32768>;
};
-&spi_clk {
- clock-frequency = <396000000>;
-};
-
&dmac0 {
status = "okay";
};
diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi
index 5f4f94ca9cc7..6992060e6a54 100644
--- a/arch/riscv/boot/dts/thead/th1520.dtsi
+++ b/arch/riscv/boot/dts/thead/th1520.dtsi
@@ -216,12 +216,6 @@ osc_32k: 32k-oscillator {
#clock-cells = <0>;
};
- spi_clk: spi-clock {
- compatible = "fixed-clock";
- clock-output-names = "spi_clk";
- #clock-cells = <0>;
- };
-
soc {
compatible = "simple-bus";
interrupt-parent = <&plic>;
@@ -256,7 +250,7 @@ spi0: spi@ffe700c000 {
compatible = "thead,th1520-spi", "snps,dw-apb-ssi";
reg = <0xff 0xe700c000 0x0 0x1000>;
interrupts = <54 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&spi_clk>;
+ clocks = <&clk CLK_SPI>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
--
2.34.1
^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [PATCH 0/6] riscv: dts: thead: Enable TH1520 AP_SUBSYS clock controller
2024-08-01 18:38 [PATCH 0/6] riscv: dts: thead: Enable TH1520 AP_SUBSYS clock controller Drew Fustini
` (5 preceding siblings ...)
2024-08-01 18:38 ` [PATCH 6/6] riscv: dts: thead: change TH1520 SPI node to use clock controller Drew Fustini
@ 2024-08-08 18:22 ` Drew Fustini
6 siblings, 0 replies; 8+ messages in thread
From: Drew Fustini @ 2024-08-08 18:22 UTC (permalink / raw)
To: Emil Renner Berthing, Thomas Bonnefille, Kanak Shilledar,
Jisheng Zhang, Guo Ren, Fu Wei, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou
Cc: linux-riscv, devicetree, linux-kernel, Drew Fustini
On Thu, Aug 01, 2024 at 11:38:04AM -0700, Drew Fustini wrote:
> This series contains the dts patches to enable the TH1520 AP_SUBSYS
> clock controller [1] and convert peripherals from fixed clocks to real
> clocks. The dt-bindings and driver patches from a previous series [2]
> have already been merged into v6.11-rc1:
>
> ae81b69fd2b1 ("clk: thead: Add support for T-Head TH1520 AP_SUBSYS clocks")
> 1037885b309c ("dt-bindings: clock: Document T-Head TH1520 AP_SUBSYS controller")
>
> [...]
Applied to thead-dt-for-next:
[1/6] riscv: dts: thead: Add TH1520 AP_SUBSYS clock controller
commit: e919fe036a97f6ed96eecf39ea61963eb2ff3442
[2/6] riscv: dts: thead: change TH1520 uart nodes to use clock controller
commit: c101b4a028e21ceaa4e39a62ee36a404d7b4bca9
[3/6] riscv: dts: thead: change TH1520 mmc nodes to use clock controller
commit: 03a20182e1e0f4a824aeef9aa7bd1d46ea6d0196
[4/6] riscv: dts: thead: update TH1520 dma and timer nodes to use clock controller
commit: 89d58327fd7451533fd313d727b50a8264477bf4
[5/6] riscv: dts: thead: add clock to TH1520 gpio nodes
commit: 7f5b28218cec55072b562be386675ccae41acca1
[6/6] riscv: dts: thead: change TH1520 SPI node to use clock controller
commit: 2d98fea7491a00dccd61fee019843b262e60f819
Best regards,
--
Drew Fustini <drew@pdp7.com>
Link: https://github.com/pdp7/linux/commits/thead-dt-for-next/
^ permalink raw reply [flat|nested] 8+ messages in thread