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From: Bjorn Helgaas <helgaas@kernel.org>
To: manivannan.sadhasivam@linaro.org
Cc: "Lorenzo Pieralisi" <lpieralisi@kernel.org>,
	"Krzysztof Wilczyński" <kw@linux.com>,
	"Rob Herring" <robh@kernel.org>,
	"Bjorn Helgaas" <bhelgaas@google.com>,
	"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
	"Conor Dooley" <conor+dt@kernel.org>,
	"Kishon Vijay Abraham I" <kishon@kernel.org>,
	"Bjorn Andersson" <andersson@kernel.org>,
	"Konrad Dybcio" <konradybcio@kernel.org>,
	linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org,
	linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
	"Konrad Dybcio" <konrad.dybcio@linaro.org>
Subject: Re: [PATCH v3 06/13] PCI: qcom-ep: Modify 'global_irq' and 'perst_irq' IRQ device names
Date: Thu, 1 Aug 2024 12:23:08 -0500	[thread overview]
Message-ID: <20240801172308.GA109178@bhelgaas> (raw)
In-Reply-To: <20240731-pci-qcom-hotplug-v3-6-a1426afdee3b@linaro.org>

On Wed, Jul 31, 2024 at 04:20:09PM +0530, Manivannan Sadhasivam via B4 Relay wrote:
> From: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> 
> Currently, the IRQ device name for both of these IRQs doesn't have Qcom
> specific prefix and PCIe domain number. This causes 2 issues:
> 
> 1. Pollutes the global IRQ namespace since 'global' is a common name.
> 2. When more than one EP controller instance is present in the SoC, naming
> conflict will occur.
> 
> Hence, add 'qcom_pcie_ep_' prefix and PCIe domain number suffix to the IRQ
> names to uniquely identify the IRQs and also to fix the above mentioned
> issues.
> 
> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> ---
>  drivers/pci/controller/dwc/pcie-qcom-ep.c | 16 ++++++++++++++--
>  1 file changed, 14 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c
> index 0bb0a056dd8f..d0a27fa6fdc8 100644
> --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c
> +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c
> @@ -711,8 +711,15 @@ static irqreturn_t qcom_pcie_ep_perst_irq_thread(int irq, void *data)
>  static int qcom_pcie_ep_enable_irq_resources(struct platform_device *pdev,
>  					     struct qcom_pcie_ep *pcie_ep)
>  {
> +	struct device *dev = pcie_ep->pci.dev;
> +	char *name;
>  	int ret;
>  
> +	name = devm_kasprintf(dev, GFP_KERNEL, "qcom_pcie_ep_global_irq%d",
> +			      pcie_ep->pci.ep.epc->domain_nr);
> +	if (!name)
> +		return -ENOMEM;

I assume this is what shows up in /proc/interrupts?  I always wonder
why it doesn't include dev_name().  A few drivers do that, but
apparently it's not universally desirable.  It's sort of annoying
that, e.g., we get a bunch of "aerdrv" interrupts with no clue which
device they relate to.

>  	pcie_ep->global_irq = platform_get_irq_byname(pdev, "global");
>  	if (pcie_ep->global_irq < 0)
>  		return pcie_ep->global_irq;
> @@ -720,18 +727,23 @@ static int qcom_pcie_ep_enable_irq_resources(struct platform_device *pdev,
>  	ret = devm_request_threaded_irq(&pdev->dev, pcie_ep->global_irq, NULL,
>  					qcom_pcie_ep_global_irq_thread,
>  					IRQF_ONESHOT,
> -					"global_irq", pcie_ep);
> +					name, pcie_ep);
>  	if (ret) {
>  		dev_err(&pdev->dev, "Failed to request Global IRQ\n");
>  		return ret;
>  	}
>  
> +	name = devm_kasprintf(dev, GFP_KERNEL, "qcom_pcie_ep_perst_irq%d",
> +			      pcie_ep->pci.ep.epc->domain_nr);
> +	if (!name)
> +		return -ENOMEM;
> +
>  	pcie_ep->perst_irq = gpiod_to_irq(pcie_ep->reset);
>  	irq_set_status_flags(pcie_ep->perst_irq, IRQ_NOAUTOEN);
>  	ret = devm_request_threaded_irq(&pdev->dev, pcie_ep->perst_irq, NULL,
>  					qcom_pcie_ep_perst_irq_thread,
>  					IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
> -					"perst_irq", pcie_ep);
> +					name, pcie_ep);
>  	if (ret) {
>  		dev_err(&pdev->dev, "Failed to request PERST IRQ\n");
>  		disable_irq(pcie_ep->global_irq);
> 
> -- 
> 2.25.1
> 
> 

  reply	other threads:[~2024-08-01 17:23 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-07-31 10:50 [PATCH v3 00/13] PCI: qcom: Enumerate endpoints based on Link up event in 'global_irq' interrupt Manivannan Sadhasivam via B4 Relay
2024-07-31 10:50 ` [PATCH v3 01/13] PCI: qcom-ep: Drop the redundant masking of global IRQ events Manivannan Sadhasivam via B4 Relay
2024-07-31 10:50 ` [PATCH v3 02/13] PCI: qcom-ep: Reword the error message for receiving unknown global IRQ event Manivannan Sadhasivam via B4 Relay
2024-07-31 10:50 ` [PATCH v3 03/13] dt-bindings: PCI: pci-ep: Update Maintainers Manivannan Sadhasivam via B4 Relay
2024-07-31 10:50 ` [PATCH v3 04/13] dt-bindings: PCI: pci-ep: Document 'linux,pci-domain' property Manivannan Sadhasivam via B4 Relay
2024-07-31 10:50 ` [PATCH v3 05/13] PCI: endpoint: Assign PCI domain number for endpoint controllers Manivannan Sadhasivam via B4 Relay
2024-08-11  1:56   ` kernel test robot
2024-08-11  2:47   ` kernel test robot
2024-08-15 15:59     ` Manivannan Sadhasivam
2024-07-31 10:50 ` [PATCH v3 06/13] PCI: qcom-ep: Modify 'global_irq' and 'perst_irq' IRQ device names Manivannan Sadhasivam via B4 Relay
2024-08-01 17:23   ` Bjorn Helgaas [this message]
2024-08-02  7:43     ` Manivannan Sadhasivam
2024-08-02 16:51       ` Bjorn Helgaas
2024-07-31 10:50 ` [PATCH v3 07/13] ARM: dts: qcom: sdx55: Add 'linux,pci-domain' to PCIe EP controller node Manivannan Sadhasivam via B4 Relay
2024-07-31 10:50 ` [PATCH v3 08/13] ARM: dts: qcom: sdx65: " Manivannan Sadhasivam via B4 Relay
2024-07-31 10:50 ` [PATCH v3 09/13] arm64: dts: qcom: sa8775p: Add 'linux,pci-domain' to PCIe EP controller nodes Manivannan Sadhasivam via B4 Relay
2024-07-31 10:50 ` [PATCH v3 10/13] dt-bindings: PCI: qcom: Add 'global' interrupt Manivannan Sadhasivam via B4 Relay
2024-07-31 10:50 ` [PATCH v3 11/13] dt-bindings: PCI: qcom,pcie-sm8450: " Manivannan Sadhasivam via B4 Relay
2024-08-06 16:54   ` Rob Herring
2024-07-31 10:50 ` [PATCH v3 12/13] PCI: qcom: Enumerate endpoints based on Link up event in 'global_irq' interrupt Manivannan Sadhasivam via B4 Relay
2024-07-31 10:50 ` [PATCH v3 13/13] arm64: dts: qcom: sm8450: Add 'global' interrupt to the PCIe RC node Manivannan Sadhasivam via B4 Relay

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