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[108.26.179.17]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1ff5929407asm71128435ad.242.2024.08.05.10.38.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Aug 2024 10:38:21 -0700 (PDT) From: Jesse Taube To: linux-riscv@lists.infradead.org Cc: Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Rob Herring , Krzysztof Kozlowski , =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Evan Green , Andrew Jones , Jesse Taube , Charlie Jenkins , Xiao Wang , Andy Chiu , Eric Biggers , Greentime Hu , =?UTF-8?q?Bj=C3=B6rn=20T=C3=B6pel?= , Heiko Stuebner , Costa Shulyupin , Andrew Morton , Baoquan He , Anup Patel , Zong Li , Sami Tolvanen , Ben Dooks , Alexandre Ghiti , "Gustavo A. R. Silva" , Erick Archer , Joel Granados , linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH 1/1] RISC-V: Add parameter to unaligned access speed Date: Mon, 5 Aug 2024 13:38:15 -0400 Message-ID: <20240805173816.3722002-1-jesse@rivosinc.com> X-Mailer: git-send-email 2.45.2 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Add a kernel parameter to the unaligned access speed. This allows skiping of the speed tests for unaligned accesses, which often is very slow. Signed-off-by: Jesse Taube --- arch/riscv/kernel/unaligned_access_speed.c | 81 ++++++++++++++++++++++ 1 file changed, 81 insertions(+) diff --git a/arch/riscv/kernel/unaligned_access_speed.c b/arch/riscv/kernel/unaligned_access_speed.c index 1548eb10ae4f..02f7a92a5fa0 100644 --- a/arch/riscv/kernel/unaligned_access_speed.c +++ b/arch/riscv/kernel/unaligned_access_speed.c @@ -400,13 +400,94 @@ static int vec_check_unaligned_access_speed_all_cpus(void *unused __always_unuse } #endif +static DEFINE_PER_CPU(long, unaligned_scalar_speed_param) = RISCV_HWPROBE_MISALIGNED_UNKNOWN; + +static int __init set_unaligned_scalar_speed_param(char *str) +{ + cpumask_var_t mask; + int ret, cpu; + long speed = RISCV_HWPROBE_MISALIGNED_UNKNOWN; + + if (!strncmp(str, "fast,", 5)) { + str += 5; + speed = RISCV_HWPROBE_MISALIGNED_FAST; + } + + if (!strncmp(str, "slow,", 5)) { + str += 5; + speed = RISCV_HWPROBE_MISALIGNED_SLOW; + } + if (speed == RISCV_HWPROBE_MISALIGNED_UNKNOWN) { + pr_warn("Invalid unaligned access speed parameter\n"); + return 1; + } + + if (!zalloc_cpumask_var(&mask, GFP_KERNEL)) + return -ENOMEM; + + ret = cpulist_parse(str, mask); + + for_each_cpu(cpu, mask) + if (per_cpu(unaligned_scalar_speed_param, cpu) == RISCV_HWPROBE_MISALIGNED_UNKNOWN) + per_cpu(unaligned_scalar_speed_param, cpu) = speed; + + free_cpumask_var(mask); + return ret == 0; +} +__setup("unaligned_scalar_speed=", set_unaligned_scalar_speed_param); + +static DEFINE_PER_CPU(long, unaligned_vector_speed_param) = RISCV_HWPROBE_VECTOR_MISALIGNED_UNKNOWN; + +static int __init set_unaligned_vector_speed_param(char *str) +{ + cpumask_var_t mask; + int ret, cpu; + long speed = RISCV_HWPROBE_VECTOR_MISALIGNED_UNKNOWN; + + if (!strncmp(str, "fast,", 5)) { + str += 5; + speed = RISCV_HWPROBE_VECTOR_MISALIGNED_FAST; + } + + if (!strncmp(str, "slow,", 5)) { + str += 5; + speed = RISCV_HWPROBE_VECTOR_MISALIGNED_SLOW; + } + if (speed == RISCV_HWPROBE_VECTOR_MISALIGNED_UNKNOWN) { + pr_warn("Invalid unaligned access speed parameter\n"); + return 1; + } + + if (!zalloc_cpumask_var(&mask, GFP_KERNEL)) + return -ENOMEM; + + ret = cpulist_parse(str, mask); + + for_each_cpu(cpu, mask) + if (per_cpu(unaligned_vector_speed_param, cpu) == RISCV_HWPROBE_VECTOR_MISALIGNED_UNKNOWN) + per_cpu(unaligned_vector_speed_param, cpu) = speed; + + free_cpumask_var(mask); + return ret == 0; +} +__setup("unaligned_vector_speed=", set_unaligned_vector_speed_param); + static int check_unaligned_access_all_cpus(void) { + int cpu; bool all_cpus_emulated, all_cpus_vec_unsupported; all_cpus_emulated = check_unaligned_access_emulated_all_cpus(); all_cpus_vec_unsupported = check_vector_unaligned_access_emulated_all_cpus(); + for_each_online_cpu(cpu) { + if (per_cpu(misaligned_access_speed, cpu) == RISCV_HWPROBE_MISALIGNED_UNKNOWN) + per_cpu(misaligned_access_speed, cpu) = per_cpu(unaligned_scalar_speed_param, cpu); + + if (per_cpu(vector_misaligned_access, cpu) == RISCV_HWPROBE_VECTOR_MISALIGNED_UNKNOWN) + per_cpu(vector_misaligned_access, cpu) = per_cpu(unaligned_vector_speed_param, cpu); + } + pr_info("\e[31m%s vector unaligned access\e[0m\n", all_cpus_vec_unsupported ? "All CPUs do not support" : "At least one cpu supports"); if (!all_cpus_vec_unsupported && -- 2.45.2