From: Conor Dooley <conor@kernel.org>
To: Linus Walleij <linus.walleij@linaro.org>
Cc: Conor Dooley <conor.dooley@microchip.com>,
linux-kernel@vger.kernel.org, Marc Zyngier <maz@kernel.org>,
Daire McNamara <daire.mcnamara@microchip.com>,
Bartosz Golaszewski <brgl@bgdev.pl>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Thomas Gleixner <tglx@linutronix.de>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
linux-riscv@lists.infradead.org, linux-gpio@vger.kernel.org,
devicetree@vger.kernel.org
Subject: Re: [RFC v7 5/6] gpio: mpfs: pass gpio line number as irq data
Date: Tue, 6 Aug 2024 18:24:24 +0100 [thread overview]
Message-ID: <20240806-baking-frustrate-32d0af5ed39c@spud> (raw)
In-Reply-To: <CACRpkdYdxdLG8=_Xd7HLwQ5+pxwGw6Xte7=UNbknB8HR474bcQ@mail.gmail.com>
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On Mon, Aug 05, 2024 at 10:11:09AM +0200, Linus Walleij wrote:
> Hi Conor,
>
> thanks for your patch!
>
> On Tue, Jul 23, 2024 at 1:28 PM Conor Dooley <conor.dooley@microchip.com> wrote:
>
> > Since the interrupt mux is going to provide us a 1:1 mapping for
> > interrupts, and it is no longer correct to hit all of the set bits in
> > the interrupt handler, store the GPIO that "owns" an interrupt in its
> > data pointer, so that we can determine which bit to clear.
> >
> > Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
>
> I don't quite get this, the irqchip of the GPIO is clearly hard-coded
> hierarchical, then why don't you:
>
> select IRQ_DOMAIN_HIERARCHY
>
> And use e.g. girq->child_to_parent_hwirq() to handle the
> hierarchy?
>
> See drivers/gpio/gpio-ixp4xx.c for a simple example of a hierarchical
> GPIO interrupt controller.
Cool, I'll check that out. I've got some re-figuring out of the
interrupt controller to do given Thomas' comment there. Maybe the
combination will solve the horrible % 32 hack...
Cheers,
Conor.
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next prev parent reply other threads:[~2024-08-06 17:24 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-07-23 11:27 [RFC v7 0/6] PolarFire SoC GPIO support Conor Dooley
2024-07-23 11:27 ` [RFC v7 1/6] dt-bindings: gpio: fix microchip,mpfs-gpio interrupt descriptions Conor Dooley
2024-07-24 13:25 ` Krzysztof Kozlowski
2024-07-24 14:29 ` Conor Dooley
2024-07-23 11:27 ` [RFC v7 2/6] dt-bindings: interrupt-controller: document PolarFire SoC's gpio interrupt mux Conor Dooley
2024-07-24 13:27 ` Krzysztof Kozlowski
2024-07-24 14:21 ` Conor Dooley
2024-07-23 11:27 ` [RFC v7 3/6] irqchip: add mpfs " Conor Dooley
2024-07-29 10:41 ` Thomas Gleixner
2024-08-01 15:09 ` Conor Dooley
2024-08-01 18:49 ` Thomas Gleixner
2024-08-02 8:08 ` Conor Dooley
2024-08-02 10:40 ` Thomas Gleixner
2024-07-23 11:27 ` [RFC v7 4/6] gpio: mpfs: add polarfire soc gpio support Conor Dooley
2024-08-05 8:00 ` Linus Walleij
2024-08-05 8:04 ` Linus Walleij
2024-08-06 17:18 ` Conor Dooley
2024-08-07 16:55 ` Linus Walleij
2024-08-07 17:22 ` Conor Dooley
2024-10-16 9:56 ` Conor Dooley
2024-10-16 10:29 ` Conor Dooley
2024-10-16 19:26 ` Linus Walleij
2024-10-16 19:42 ` Conor Dooley
2024-10-22 16:28 ` Conor Dooley
2024-10-23 9:58 ` Linus Walleij
2024-10-16 19:25 ` Linus Walleij
2024-07-23 11:27 ` [RFC v7 5/6] gpio: mpfs: pass gpio line number as irq data Conor Dooley
2024-08-05 8:11 ` Linus Walleij
2024-08-06 17:24 ` Conor Dooley [this message]
2024-07-23 11:27 ` [RFC v7 6/6] riscv: dts: microchip: update gpio interrupts to better match the SoC Conor Dooley
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