From: Conor Dooley <conor@kernel.org>
To: Charlie Jenkins <charlie@rivosinc.com>
Cc: Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Jisheng Zhang <jszhang@kernel.org>, Chen-Yu Tsai <wens@csie.org>,
Jernej Skrabec <jernej.skrabec@gmail.com>,
Samuel Holland <samuel@sholland.org>,
Samuel Holland <samuel.holland@sifive.com>,
Jonathan Corbet <corbet@lwn.net>, Shuah Khan <shuah@kernel.org>,
Guo Ren <guoren@kernel.org>, Evan Green <evan@rivosinc.com>,
Andy Chiu <andy.chiu@sifive.com>,
Jessica Clarke <jrtc27@jrtc27.com>,
Andrew Jones <ajones@ventanamicro.com>,
linux-riscv@lists.infradead.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-sunxi@lists.linux.dev,
linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org,
Conor Dooley <conor.dooley@microchip.com>,
Heiko Stuebner <heiko@sntech.de>
Subject: Re: [PATCH v9 00/13] riscv: Add support for xtheadvector
Date: Tue, 20 Aug 2024 17:42:12 +0100 [thread overview]
Message-ID: <20240820-computer-viewable-eef06bef1bea@spud> (raw)
In-Reply-To: <ZsPP4GMwPVBfq+fL@ghost>
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On Mon, Aug 19, 2024 at 04:06:08PM -0700, Charlie Jenkins wrote:
> On Tue, Aug 13, 2024 at 04:55:27PM +0100, Conor Dooley wrote:
> > On Mon, Aug 12, 2024 at 05:45:30PM -0700, Charlie Jenkins wrote:
> > > On Fri, Aug 09, 2024 at 11:31:15PM +0100, Conor Dooley wrote:
> > > > On Tue, Aug 06, 2024 at 05:31:36PM -0700, Charlie Jenkins wrote:
> > > > > xtheadvector is a custom extension that is based upon riscv vector
> > > > > version 0.7.1 [1]. All of the vector routines have been modified to
> > > > > support this alternative vector version based upon whether xtheadvector
> > > > > was determined to be supported at boot.
> > > > >
> > > > > vlenb is not supported on the existing xtheadvector hardware, so a
> > > > > devicetree property thead,vlenb is added to provide the vlenb to Linux.
> > > > >
> > > > > There is a new hwprobe key RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0 that is
> > > > > used to request which thead vendor extensions are supported on the
> > > > > current platform. This allows future vendors to allocate hwprobe keys
> > > > > for their vendor.
> > > > >
> > > > > Support for xtheadvector is also added to the vector kselftests.
> > > >
> > > > So uh, since noone seems to have brought it up, in the light of the issues
> > > > with thead's vector implementation, (https://ghostwriteattack.com/) do we
> > > > want to enable it at all?
> > >
> > > I can make it clear in the kconfig that xtheadvector is succeptible to
> > > this attack and that it should be enabled with caution. I think we
> > > should let people that understand the risk to enable it.
> >
> > I think the clearest way might be "depends on BROKEN"?
>
> Sorry for the delay, I am not sure if BROKEN is the best way of doing
> this. There is the generic CPU_MITIGATIONS config that I think we should
> use to handle this at boot time. This would allow generic kernels to be
> used on the platform, but a kernel config of "mitigations=off" would
> allow xtheadvector to be enabled. I'll look into this a bit more and
> send out a patch. Palmer merged a patch into for-next to enable
> GENERIC_CPU_VULNERABILITIES for riscv so I will add ghostwrite there
> as well.
Palmer also pointed out to me last week that not all implementations of
xtheadvector actually have the flaw, so it makes sense to not depend on
BROKEN. We should figure out exactly which CPUs are and are not
vulnerable (Guo Ren hopefully will know) and permit enabling it without
"mitagations=off" on the CPUs that are not vulnerable.
Thanks,
Conor.
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prev parent reply other threads:[~2024-08-20 16:42 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-08-07 0:31 [PATCH v9 00/13] riscv: Add support for xtheadvector Charlie Jenkins
2024-08-07 0:31 ` [PATCH v9 01/13] dt-bindings: riscv: Add xtheadvector ISA extension description Charlie Jenkins
2024-08-07 0:31 ` [PATCH v9 02/13] dt-bindings: cpus: add a thead vlen register length property Charlie Jenkins
2024-08-07 0:31 ` [PATCH v9 03/13] riscv: dts: allwinner: Add xtheadvector to the D1/D1s devicetree Charlie Jenkins
2024-08-07 0:31 ` [PATCH v9 04/13] riscv: Add thead and xtheadvector as a vendor extension Charlie Jenkins
2024-08-07 0:31 ` [PATCH v9 05/13] riscv: vector: Use vlenb from DT for thead Charlie Jenkins
2024-08-07 0:31 ` [PATCH v9 06/13] RISC-V: define the elements of the VCSR vector CSR Charlie Jenkins
2024-08-07 0:31 ` [PATCH v9 07/13] riscv: csr: Add CSR encodings for CSR_VXRM/CSR_VXSAT Charlie Jenkins
2024-08-07 0:31 ` [PATCH v9 08/13] riscv: Add xtheadvector instruction definitions Charlie Jenkins
2024-08-07 0:31 ` [PATCH v9 09/13] riscv: vector: Support xtheadvector save/restore Charlie Jenkins
2024-08-07 0:31 ` [PATCH v9 10/13] riscv: hwprobe: Add thead vendor extension probing Charlie Jenkins
2024-08-07 0:31 ` [PATCH v9 11/13] riscv: hwprobe: Document thead vendor extensions and xtheadvector extension Charlie Jenkins
2024-08-07 0:31 ` [PATCH v9 12/13] selftests: riscv: Fix vector tests Charlie Jenkins
2024-08-07 0:31 ` [PATCH v9 13/13] selftests: riscv: Support xtheadvector in " Charlie Jenkins
2024-08-09 22:31 ` [PATCH v9 00/13] riscv: Add support for xtheadvector Conor Dooley
2024-08-13 0:45 ` Charlie Jenkins
2024-08-13 15:55 ` Conor Dooley
2024-08-19 23:06 ` Charlie Jenkins
2024-08-20 16:42 ` Conor Dooley [this message]
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