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AJvYcCUztTf+tsR0HXCZKl4NddoOoiiSofXW60sV3RLWZkrYKayvvlqjCnlYIMmcsR+GP4+bjJjGHOnl0sTG@vger.kernel.org X-Gm-Message-State: AOJu0YyXoflH5HbLj4K1cyGsDuCM0GuTg71Hj0xom8D5jOYcIVCBZw6i dl/uxiEUZ3D4tk/0t7vWmjLDyi71B6XyMSDcRvczcimZ0M2esHhrj9GGvet6Eg== X-Google-Smtp-Source: AGHT+IEg701oVGHlnE52pK3OQhbcRTjhhzAp3dBmqRMQAHDvR10F57i/IZHuH1pve1bxSwuJqV6lAQ== X-Received: by 2002:a17:90b:4b01:b0:2d3:ce8d:f7f1 with SMTP id 98e67ed59e1d1-2d8561c7556mr6135729a91.25.1725006960007; Fri, 30 Aug 2024 01:36:00 -0700 (PDT) Received: from thinkpad ([117.193.213.95]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2d85b39ce64sm3134091a91.39.2024.08.30.01.35.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Aug 2024 01:35:59 -0700 (PDT) Date: Fri, 30 Aug 2024 14:05:51 +0530 From: Manivannan Sadhasivam To: Sricharan R Cc: bhelgaas@google.com, lpieralisi@kernel.org, kw@linux.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, vkoul@kernel.org, kishon@kernel.org, andersson@kernel.org, konradybcio@kernel.org, p.zabel@pengutronix.de, dmitry.baryshkov@linaro.org, quic_nsekar@quicinc.com, linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, robimarko@gmail.com Subject: Re: [PATCH V2 2/6] dt-bindings: PCI: qcom: Add IPQ5108 SoC Message-ID: <20240830083551.yazww3kj2shf4ocq@thinkpad> References: <20240827045757.1101194-1-quic_srichara@quicinc.com> <20240827045757.1101194-3-quic_srichara@quicinc.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20240827045757.1101194-3-quic_srichara@quicinc.com> On Tue, Aug 27, 2024 at 10:27:53AM +0530, Sricharan R wrote: > From: Nitheesh Sekar > > Add support for the PCIe controller on the Qualcomm > IPQ5108 SoC to the bindings. > > Reviewed-by: Krzysztof Kozlowski > Signed-off-by: Nitheesh Sekar > Signed-off-by: Sricharan Ramabadhran Reviewed-by: Manivannan Sadhasivam - Mani > --- > [v2] Added reviewed by tag > > .../devicetree/bindings/pci/qcom,pcie.yaml | 35 +++++++++++++++++++ > 1 file changed, 35 insertions(+) > > diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml > index f867746b1ae5..c12efa27b8d8 100644 > --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml > +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml > @@ -21,6 +21,7 @@ properties: > - qcom,pcie-apq8064 > - qcom,pcie-apq8084 > - qcom,pcie-ipq4019 > + - qcom,pcie-ipq5018 > - qcom,pcie-ipq6018 > - qcom,pcie-ipq8064 > - qcom,pcie-ipq8064-v2 > @@ -312,6 +313,39 @@ allOf: > - const: ahb # AHB reset > - const: phy_ahb # PHY AHB reset > > + - if: > + properties: > + compatible: > + contains: > + enum: > + - qcom,pcie-ipq5018 > + then: > + properties: > + clocks: > + minItems: 6 > + maxItems: 6 > + clock-names: > + items: > + - const: iface # PCIe to SysNOC BIU clock > + - const: axi_m # AXI Master clock > + - const: axi_s # AXI Slave clock > + - const: ahb # AHB clock > + - const: aux # Auxiliary clock > + - const: axi_bridge # AXI bridge clock > + resets: > + minItems: 8 > + maxItems: 8 > + reset-names: > + items: > + - const: pipe # PIPE reset > + - const: sleep # Sleep reset > + - const: sticky # Core sticky reset > + - const: axi_m # AXI master reset > + - const: axi_s # AXI slave reset > + - const: ahb # AHB reset > + - const: axi_m_sticky # AXI master sticky reset > + - const: axi_s_sticky # AXI slave sticky reset > + > - if: > properties: > compatible: > @@ -503,6 +537,7 @@ allOf: > enum: > - qcom,pcie-apq8064 > - qcom,pcie-ipq4019 > + - qcom,pcie-ipq5018 > - qcom,pcie-ipq8064 > - qcom,pcie-ipq8064v2 > - qcom,pcie-ipq8074 > -- > 2.34.1 > -- மணிவண்ணன் சதாசிவம்