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AJvYcCV10km+7oaE3482Tgufd7+FMybxWgjLIAZnBHW5p7has30WXhqq9VdM/m9vkWCWZvrJdDZafQxUKBCP@vger.kernel.org X-Gm-Message-State: AOJu0YyUG6MYSTaNhmRP7q0IqnHtINXQurltcAO+IE++upNOJ/NwcCI1 6ENtjmSdUgXUBqJZbuvDYnqzo/xPVrG1RnW3YNLSNdL/tXSPAxGtAwv9h/MxWw== X-Google-Smtp-Source: AGHT+IGJE/0+ObI0CkZ+IOdkM1nwpEnemU7pt2j1Bs59c55j95S6Wc2rMVcunwSLXz0CAPYJaOw1vg== X-Received: by 2002:a05:6808:1242:b0:3d9:384a:7e1a with SMTP id 5614622812f47-3df05c4e59amr5026350b6e.1.1725008350377; Fri, 30 Aug 2024 01:59:10 -0700 (PDT) Received: from thinkpad ([117.193.213.95]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-7d22e9d721dsm2512363a12.87.2024.08.30.01.59.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Aug 2024 01:59:10 -0700 (PDT) Date: Fri, 30 Aug 2024 14:29:01 +0530 From: Manivannan Sadhasivam To: Sricharan R Cc: bhelgaas@google.com, lpieralisi@kernel.org, kw@linux.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, vkoul@kernel.org, kishon@kernel.org, andersson@kernel.org, konradybcio@kernel.org, p.zabel@pengutronix.de, dmitry.baryshkov@linaro.org, quic_nsekar@quicinc.com, linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, robimarko@gmail.com Subject: Re: [PATCH V2 5/6] arm64: dts: qcom: ipq5018: Add PCIe related nodes Message-ID: <20240830085901.oeiuuijlvq2ydho2@thinkpad> References: <20240827045757.1101194-1-quic_srichara@quicinc.com> <20240827045757.1101194-6-quic_srichara@quicinc.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20240827045757.1101194-6-quic_srichara@quicinc.com> On Tue, Aug 27, 2024 at 10:27:56AM +0530, Sricharan R wrote: > From: Nitheesh Sekar > > Add phy and controller nodes for a 2-lane Gen2 and > 1-lane Gen2 PCIe buses. > > Signed-off-by: Nitheesh Sekar > Signed-off-by: Sricharan R > --- > [v2] Removed relocatable flags, removed assigned-clock-rates, > fixed rest of the cosmetic comments. > > arch/arm64/boot/dts/qcom/ipq5018.dtsi | 168 +++++++++++++++++++++++++- > 1 file changed, 166 insertions(+), 2 deletions(-) > > diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi > index 7e6e2c121979..dd5d6b7ff094 100644 > --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi > +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi > @@ -9,6 +9,7 @@ > #include > #include > #include > +#include > > / { > interrupt-parent = <&intc>; > @@ -143,7 +144,33 @@ usbphy0: phy@5b000 { > resets = <&gcc GCC_QUSB2_0_PHY_BCR>; > > #phy-cells = <0>; > + }; > + > + pcie_x1phy: phy@7e000{ > + compatible = "qcom,ipq5018-uniphy-pcie-gen2x1"; > + reg = <0x0007e000 0x800>; > + #phy-cells = <0>; > + #clock-cells = <0>; > + clocks = <&gcc GCC_PCIE1_PIPE_CLK>; > + clock-names = "pipe"; > + assigned-clocks = <&gcc GCC_PCIE1_PIPE_CLK>; > + resets = <&gcc GCC_PCIE1_PHY_BCR>, > + <&gcc GCC_PCIE1PHY_PHY_BCR>; > + reset-names = "phy", "common"; > + status = "disabled"; > + }; > > + pcie_x2phy: phy@86000{ > + compatible = "qcom,ipq5018-uniphy-pcie-gen2x2"; > + reg = <0x00086000 0x1000>; > + #phy-cells = <0>; > + #clock-cells = <0>; > + clocks = <&gcc GCC_PCIE0_PIPE_CLK>; > + clock-names = "pipe"; > + assigned-clocks = <&gcc GCC_PCIE0_PIPE_CLK>; > + resets = <&gcc GCC_PCIE0_PHY_BCR>, > + <&gcc GCC_PCIE0PHY_PHY_BCR>; > + reset-names = "phy", "common"; > status = "disabled"; > }; > > @@ -170,8 +197,8 @@ gcc: clock-controller@1800000 { > reg = <0x01800000 0x80000>; > clocks = <&xo_board_clk>, > <&sleep_clk>, > - <0>, > - <0>, > + <&pcie_x2phy>, > + <&pcie_x1phy>, > <0>, > <0>, > <0>, > @@ -387,6 +414,143 @@ frame@b128000 { > status = "disabled"; > }; > }; > + > + pcie0: pci@80000000 { pcie@ > + compatible = "qcom,pcie-ipq5018"; > + reg = <0x80000000 0xf1d>, > + <0x80000f20 0xa8>, > + <0x80001000 0x1000>, > + <0x00078000 0x3000>, > + <0x80100000 0x1000>; Are you sure that the config space is only 4K? > + reg-names = "dbi", "elbi", "atu", "parf", "config"; > + device_type = "pci"; > + linux,pci-domain = <0>; > + bus-range = <0x00 0xff>; > + num-lanes = <1>; > + max-link-speed = <2>; > + #address-cells = <3>; > + #size-cells = <2>; > + > + phys = <&pcie_x1phy>; > + phy-names ="pciephy"; > + > + ranges = <0x01000000 0 0x80200000 0x80200000 0 0x00100000 Please check the value of this field in other SoCs. > + 0x02000000 0 0x80300000 0x80300000 0 0x10000000>; > + > + #interrupt-cells = <1>; > + interrupt-map-mask = <0 0 0 0x7>; > + interrupt-map = <0 0 0 1 &intc 0 0 142 IRQ_TYPE_LEVEL_HIGH>, > + <0 0 0 2 &intc 0 0 143 IRQ_TYPE_LEVEL_HIGH>, > + <0 0 0 3 &intc 0 0 144 IRQ_TYPE_LEVEL_HIGH>, > + <0 0 0 4 &intc 0 0 145 IRQ_TYPE_LEVEL_HIGH>; > + > + interrupts = ; > + interrupt-names = "global_irq"; I'm pretty sure that this SoC has SPI based MSI interrupts. So they should be described even though ITS is supported. > + > + clocks = <&gcc GCC_SYS_NOC_PCIE1_AXI_CLK>, > + <&gcc GCC_PCIE1_AXI_M_CLK>, > + <&gcc GCC_PCIE1_AXI_S_CLK>, > + <&gcc GCC_PCIE1_AHB_CLK>, > + <&gcc GCC_PCIE1_AUX_CLK>, > + <&gcc GCC_PCIE1_AXI_S_BRIDGE_CLK>; > + > + clock-names = "iface", > + "axi_m", > + "axi_s", > + "ahb", > + "aux", > + "axi_bridge"; > + > + resets = <&gcc GCC_PCIE1_PIPE_ARES>, > + <&gcc GCC_PCIE1_SLEEP_ARES>, > + <&gcc GCC_PCIE1_CORE_STICKY_ARES>, > + <&gcc GCC_PCIE1_AXI_MASTER_ARES>, > + <&gcc GCC_PCIE1_AXI_SLAVE_ARES>, > + <&gcc GCC_PCIE1_AHB_ARES>, > + <&gcc GCC_PCIE1_AXI_MASTER_STICKY_ARES>, > + <&gcc GCC_PCIE1_AXI_SLAVE_STICKY_ARES>; > + > + reset-names = "pipe", > + "sleep", > + "sticky", > + "axi_m", > + "axi_s", > + "ahb", > + "axi_m_sticky", > + "axi_s_sticky"; > + > + msi-map = <0x0 &v2m0 0x0 0xff8>; > + status = "disabled"; Please add the rootport node also as like other SoCs. Above comments applies to below PCIe node. - Mani > + }; > + > + pcie1: pci@a0000000 { > + compatible = "qcom,pcie-ipq5018"; > + reg = <0xa0000000 0xf1d>, > + <0xa0000f20 0xa8>, > + <0xa0001000 0x1000>, > + <0x00080000 0x3000>, > + <0xa0100000 0x1000>; > + reg-names = "dbi", "elbi", "atu", "parf", "config"; > + device_type = "pci"; > + linux,pci-domain = <1>; > + bus-range = <0x00 0xff>; > + num-lanes = <2>; > + max-link-speed = <2>; > + #address-cells = <3>; > + #size-cells = <2>; > + > + phys = <&pcie_x2phy>; > + phy-names ="pciephy"; > + > + ranges = <0x01000000 0 0xa0200000 0xa0200000 0 0x00100000 > + 0x02000000 0 0xa0300000 0xa0300000 0 0x10000000>; > + > + #interrupt-cells = <1>; > + interrupt-map-mask = <0 0 0 0x7>; > + interrupt-map = <0 0 0 1 &intc 0 0 75 IRQ_TYPE_LEVEL_HIGH>, > + <0 0 0 2 &intc 0 0 78 IRQ_TYPE_LEVEL_HIGH>, > + <0 0 0 3 &intc 0 0 79 IRQ_TYPE_LEVEL_HIGH>, > + <0 0 0 4 &intc 0 0 83 IRQ_TYPE_LEVEL_HIGH>; > + > + interrupts = ; > + interrupt-names = "global_irq"; > + > + clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>, > + <&gcc GCC_PCIE0_AXI_M_CLK>, > + <&gcc GCC_PCIE0_AXI_S_CLK>, > + <&gcc GCC_PCIE0_AHB_CLK>, > + <&gcc GCC_PCIE0_AUX_CLK>, > + <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>; > + > + clock-names = "iface", > + "axi_m", > + "axi_s", > + "ahb", > + "aux", > + "axi_bridge"; > + > + resets = <&gcc GCC_PCIE0_PIPE_ARES>, > + <&gcc GCC_PCIE0_SLEEP_ARES>, > + <&gcc GCC_PCIE0_CORE_STICKY_ARES>, > + <&gcc GCC_PCIE0_AXI_MASTER_ARES>, > + <&gcc GCC_PCIE0_AXI_SLAVE_ARES>, > + <&gcc GCC_PCIE0_AHB_ARES>, > + <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>, > + <&gcc GCC_PCIE0_AXI_SLAVE_STICKY_ARES>; > + > + reset-names = "pipe", > + "sleep", > + "sticky", > + "axi_m", > + "axi_s", > + "ahb", > + "axi_m_sticky", > + "axi_s_sticky"; > + > + msi-map = <0x0 &v2m0 0x0 0xff8>; > + status = "disabled"; > + }; > + > }; > > timer { > -- > 2.34.1 > -- மணிவண்ணன் சதாசிவம்