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AJvYcCWBJW3r/oK881WZjQngBEi6qeuQ3FXfJvEB7QgjjlCLW/7nrZxjjD/U7Uyr5MIOhFYpfYEsyF9evg40@vger.kernel.org X-Gm-Message-State: AOJu0YwEnru6vdvlgEv7yx3S8Qx77E6d9xqgVYHXz2GXsE92Uj8c04Ol YU4DHWiHwsF4SIShRqGIWBjPAWZdu58nw3HMfQyXvR/IQlMmLmN3FiQpJwSJmw== X-Google-Smtp-Source: AGHT+IEFIR4WehLNVjGEUs2gw5mnU3QWqaSdoqihZp/g8nHwvyMPpHyoucyIC0wG1iBpyPhz8/rbSw== X-Received: by 2002:a05:6a00:234a:b0:714:1fc3:79f7 with SMTP id d2e1a72fcca58-715dfc506a0mr8912395b3a.17.1725035629373; Fri, 30 Aug 2024 09:33:49 -0700 (PDT) Received: from thinkpad ([117.193.213.95]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-7d22e9daac4sm2763284a12.92.2024.08.30.09.33.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Aug 2024 09:33:48 -0700 (PDT) Date: Fri, 30 Aug 2024 22:03:41 +0530 From: Manivannan Sadhasivam To: Thippeswamy Havalige Cc: bhelgaas@google.com, lpieralisi@kernel.org, kw@linux.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, michal.simek@amd.com, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v4 2/2] PCI: xilinx-xdma: Add Xilinx QDMA Root Port driver Message-ID: <20240830163341.437jztschfrstrrj@thinkpad> References: <20240811022345.1178203-1-thippesw@amd.com> <20240811022345.1178203-3-thippesw@amd.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20240811022345.1178203-3-thippesw@amd.com> On Sun, Aug 11, 2024 at 07:53:45AM +0530, Thippeswamy Havalige wrote: > Add support for Xilinx QDMA Soft IP core as Root Port. > > The Versal Prime devices support QDMA soft IP module in programmable logic. > > The integrated QDMA Soft IP block has integrated bridge function that can > act as PCIe Root Port. > > Signed-off-by: Thippeswamy Havalige One comment below. With that addressed, Reviewed-by: Manivannan Sadhasivam > --- > drivers/pci/controller/pcie-xilinx-dma-pl.c | 54 ++++++++++++++++++++- > 1 file changed, 53 insertions(+), 1 deletion(-) > --- > changes in v4: > - none > > changes in v3: > - Modify macro value to lower case. > - Change return type based QDMA compatible. > > changes in v2: > - Add description for struct pl_dma_pcie > --- > diff --git a/drivers/pci/controller/pcie-xilinx-dma-pl.c b/drivers/pci/controller/pcie-xilinx-dma-pl.c > index 5be5dfd8398f..1ea6a1d265bb 100644 > --- a/drivers/pci/controller/pcie-xilinx-dma-pl.c > +++ b/drivers/pci/controller/pcie-xilinx-dma-pl.c > @@ -13,6 +13,7 @@ > #include > #include > #include > +#include Looks like this header is not used. - Mani > > #include "../pci.h" > #include "pcie-xilinx-common.h" > @@ -71,10 +72,24 @@ > > /* Phy Status/Control Register definitions */ > #define XILINX_PCIE_DMA_REG_PSCR_LNKUP BIT(11) > +#define QDMA_BRIDGE_BASE_OFF 0xcd8 > > /* Number of MSI IRQs */ > #define XILINX_NUM_MSI_IRQS 64 > > +enum xilinx_pl_dma_version { > + XDMA, > + QDMA, > +}; > + > +/** > + * struct xilinx_pl_dma_variant - PL DMA PCIe variant information > + * @version: DMA version > + */ > +struct xilinx_pl_dma_variant { > + enum xilinx_pl_dma_version version; > +}; > + > struct xilinx_msi { > struct irq_domain *msi_domain; > unsigned long *bitmap; > @@ -88,6 +103,7 @@ struct xilinx_msi { > * struct pl_dma_pcie - PCIe port information > * @dev: Device pointer > * @reg_base: IO Mapped Register Base > + * @cfg_base: IO Mapped Configuration Base > * @irq: Interrupt number > * @cfg: Holds mappings of config space window > * @phys_reg_base: Physical address of reg base > @@ -97,10 +113,12 @@ struct xilinx_msi { > * @msi: MSI information > * @intx_irq: INTx error interrupt number > * @lock: Lock protecting shared register access > + * @variant: PL DMA PCIe version check pointer > */ > struct pl_dma_pcie { > struct device *dev; > void __iomem *reg_base; > + void __iomem *cfg_base; > int irq; > struct pci_config_window *cfg; > phys_addr_t phys_reg_base; > @@ -110,16 +128,23 @@ struct pl_dma_pcie { > struct xilinx_msi msi; > int intx_irq; > raw_spinlock_t lock; > + const struct xilinx_pl_dma_variant *variant; > }; > > static inline u32 pcie_read(struct pl_dma_pcie *port, u32 reg) > { > + if (port->variant->version == QDMA) > + return readl(port->reg_base + reg + QDMA_BRIDGE_BASE_OFF); > + > return readl(port->reg_base + reg); > } > > static inline void pcie_write(struct pl_dma_pcie *port, u32 val, u32 reg) > { > - writel(val, port->reg_base + reg); > + if (port->variant->version == QDMA) > + writel(val, port->reg_base + reg + QDMA_BRIDGE_BASE_OFF); > + else > + writel(val, port->reg_base + reg); > } > > static inline bool xilinx_pl_dma_pcie_link_up(struct pl_dma_pcie *port) > @@ -173,6 +198,9 @@ static void __iomem *xilinx_pl_dma_pcie_map_bus(struct pci_bus *bus, > if (!xilinx_pl_dma_pcie_valid_device(bus, devfn)) > return NULL; > > + if (port->variant->version == QDMA) > + return port->cfg_base + PCIE_ECAM_OFFSET(bus->number, devfn, where); > + > return port->reg_base + PCIE_ECAM_OFFSET(bus->number, devfn, where); > } > > @@ -731,6 +759,15 @@ static int xilinx_pl_dma_pcie_parse_dt(struct pl_dma_pcie *port, > > port->reg_base = port->cfg->win; > > + if (port->variant->version == QDMA) { > + port->cfg_base = port->cfg->win; > + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "breg"); > + port->reg_base = devm_ioremap_resource(dev, res); > + if (IS_ERR(port->reg_base)) > + return PTR_ERR(port->reg_base); > + port->phys_reg_base = res->start; > + } > + > err = xilinx_request_msi_irq(port); > if (err) { > pci_ecam_free(port->cfg); > @@ -760,6 +797,8 @@ static int xilinx_pl_dma_pcie_probe(struct platform_device *pdev) > if (!bus) > return -ENODEV; > > + port->variant = of_device_get_match_data(dev); > + > err = xilinx_pl_dma_pcie_parse_dt(port, bus->res); > if (err) { > dev_err(dev, "Parsing DT failed\n"); > @@ -791,9 +830,22 @@ static int xilinx_pl_dma_pcie_probe(struct platform_device *pdev) > return err; > } > > +static const struct xilinx_pl_dma_variant xdma_host = { > + .version = XDMA, > +}; > + > +static const struct xilinx_pl_dma_variant qdma_host = { > + .version = QDMA, > +}; > + > static const struct of_device_id xilinx_pl_dma_pcie_of_match[] = { > { > .compatible = "xlnx,xdma-host-3.00", > + .data = &xdma_host, > + }, > + { > + .compatible = "xlnx,qdma-host-3.00", > + .data = &qdma_host, > }, > {} > }; > -- > 2.34.1 > > -- மணிவண்ணன் சதாசிவம்