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[209.17.68.221]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2051553648fsm54619285ad.172.2024.09.01.10.47.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 01 Sep 2024 10:47:53 -0700 (PDT) Date: Mon, 2 Sep 2024 02:47:52 +0900 From: Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= To: manivannan.sadhasivam@linaro.org Cc: Lorenzo Pieralisi , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Kishon Vijay Abraham I , Bjorn Andersson , Konrad Dybcio , linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio Subject: Re: [PATCH v4 00/12] PCI: qcom: Enumerate endpoints based on Link up event in 'global_irq' interrupt Message-ID: <20240901174752.GL235729@rocinante> References: <20240828-pci-qcom-hotplug-v4-0-263a385fbbcb@linaro.org> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20240828-pci-qcom-hotplug-v4-0-263a385fbbcb@linaro.org> Hello, > This series adds support to enumerate the PCIe endpoint devices using the Qcom > specific 'Link up' event in 'global' IRQ. Historically, Qcom PCIe RC controllers > lacked standard hotplug support. So when an endpoint is attached to the SoC, > users have to rescan the bus manually to enumerate the device. But this can be > avoided by rescanning the bus upon receiving 'Link up' event. > > Qcom PCIe RC controllers are capable of generating the 'global' SPI interrupt > to the host CPUs. The device driver can use this interrupt to identify events > such as PCIe link specific events, safety events etc... > > One such event is the PCIe Link up event generated when an endpoint is detected > on the bus and the Link is 'up'. This event can be used to enumerate the > endpoint devices. > > So add support for capturing the PCIe Link up event using the 'global' interrupt > in the driver. Once the Link up event is received, the bus underneath the host > bridge is scanned to enumerate PCIe endpoint devices. > > This series also has some cleanups to the Qcom PCIe EP controller driver for > interrupt handling. > > NOTE: During v2 review, there was a discussion about removing the devices when > 'Link Down' event is received. But this needs some more investigation, so I'm > planning to add it later. > > Testing > ======= > > This series is tested on Qcom SM8450 based development board that has 2 SoCs > connected over PCIe. > > Merging Strategy > ================ > > I'm expecting the binding and PCI driver changes to go through PCI tree and DTS > patches through Qcom tree. Applied to controller/qcom, thank you! [01/08] PCI: qcom-ep: Drop the redundant masking of global IRQ events https://git.kernel.org/pci/pci/c/3858e8a5ea71 [02/08] PCI: qcom-ep: Reword the error message for receiving unknown global IRQ event https://git.kernel.org/pci/pci/c/95bebcbd657c [03/08] dt-bindings: PCI: pci-ep: Update Maintainers https://git.kernel.org/pci/pci/c/99244b999dec [04/08] dt-bindings: PCI: pci-ep: Document 'linux,pci-domain' property https://git.kernel.org/pci/pci/c/ada94d00620a [05/08] PCI: endpoint: Assign PCI domain number for endpoint controllers https://git.kernel.org/pci/pci/c/0328947c5032 [06/08] PCI: qcom-ep: Modify 'global_irq' and 'perst_irq' IRQ device names https://git.kernel.org/pci/pci/c/bba1251edf85 [07/08] dt-bindings: PCI: qcom,pcie-sm8450: Add 'global' interrupt https://git.kernel.org/pci/pci/c/6efd853303a5 [08/08] PCI: qcom: Enumerate endpoints based on Link up event in 'global_irq' interrupt https://git.kernel.org/pci/pci/c/4581403f6792 Krzysztof