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[209.17.68.221]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-715e5749b51sm5585952b3a.184.2024.09.01.11.01.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 01 Sep 2024 11:01:39 -0700 (PDT) Date: Mon, 2 Sep 2024 03:01:37 +0900 From: Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= To: Jim Quinlan Cc: linux-pci@vger.kernel.org, Nicolas Saenz Julienne , Bjorn Helgaas , Lorenzo Pieralisi , Cyril Brulebois , Stanimir Varbanov , Manivannan Sadhasivam , Krzysztof Kozlowski , bcm-kernel-feedback-list@broadcom.com, jim2101024@gmail.com, "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , "moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE" , open list , "moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE" , Rob Herring Subject: Re: [PATCH v6 00/13] PCI: brcnstb: Enable STB 7712 SOC Message-ID: <20240901180137.GN235729@rocinante> References: <20240815225731.40276-1-james.quinlan@broadcom.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20240815225731.40276-1-james.quinlan@broadcom.com> Hello, > This submission is for the Broadcom STB 7712, sibling SOC of the RPi5 chip. > Stanimir has already submitted a patch "Add PCIe support for bcm2712" for > the RPi version of the SOC. It is hoped that Stanimir will allow us to > submit this series first and subsequently rebase his patch(es). > > The largest commit, "Refactor for chips with many regular inbound BARs" > affects both the STB and RPi SOCs. It allows for multiple inbound ranges > where previously only one was effectively used. This feature will also > be present in future STB chips, as well as Broadcom's Cable Modem group. Applied to controller/brcmstb, thank you! [01/13] dt-bindings: PCI: brcm,stb-pcie: Change brcmstb maintainer and cleanup https://git.kernel.org/pci/pci/c/2cd86a7c2346 [02/13] dt-bindings: PCI: brcm,stb-pcie: Use maxItems for reset controllers https://git.kernel.org/pci/pci/c/9014c6b92fbe [03/13] dt-bindings: PCI: brcm,stb-pcie: Add 7712 SoC description https://git.kernel.org/pci/pci/c/154051eae687 [04/13] PCI: brcmstb: Use common error handling code in brcm_pcie_probe() https://git.kernel.org/pci/pci/c/5ccf0ade7937 [05/13] PCI: brcmstb: Use bridge reset if available https://git.kernel.org/pci/pci/c/996a76b913ab [06/13] PCI: brcmstb: Use swinit reset if available https://git.kernel.org/pci/pci/c/50fd71c2d2fb [07/13] PCI: brcmstb: PCI: brcmstb: Make HARD_DEBUG, INTR2_CPU_BASE offsets SoC-specific https://git.kernel.org/pci/pci/c/e42c556de029 [08/13] PCI: brcmstb: Remove two unused constants from driver https://git.kernel.org/pci/pci/c/092001a4ebd0 [09/13] PCI: brcmstb: Don't conflate the reset rescal with PHY ctrl https://git.kernel.org/pci/pci/c/1bed07ffeccb [10/13] PCI: brcmstb: Refactor for chips with many regular inbound windows https://git.kernel.org/pci/pci/c/22877c1ac638 [11/13] PCI: brcmstb: Check return value of all reset_control_* calls https://git.kernel.org/pci/pci/c/363051fc3ab8 [12/13] PCI: brcmstb: Change field name from 'type' to 'soc_base' https://git.kernel.org/pci/pci/c/e78bade02796 [13/13] PCI: brcmstb: Enable 7712 SOCs https://git.kernel.org/pci/pci/c/1ae791a877e7 Krzysztof