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[209.17.68.221]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-7d4fbd8c61asm1526789a12.25.2024.09.04.07.37.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Sep 2024 07:37:35 -0700 (PDT) Date: Wed, 4 Sep 2024 23:37:34 +0900 From: Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= To: Krzysztof Kozlowski Cc: Xiaowei Song , Binghui Wang , Bjorn Helgaas , Lorenzo Pieralisi , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Marek Vasut , Yoshihiro Shimoda , Kunihiko Hayashi , Masami Hiramatsu , Geert Uytterhoeven , Magnus Damm , linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH 1/3] dt-bindings: PCI: hisilicon,kirin-pcie: add top-level constraints Message-ID: <20240904143734.GA3032973@rocinante> References: <20240818172843.121787-1-krzysztof.kozlowski@linaro.org> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20240818172843.121787-1-krzysztof.kozlowski@linaro.org> Hello, > Properties with variable number of items per each device are expected to > have widest constraints in top-level "properties:" block and further > customized (narrowed) in "if:then:". Add missing top-level constraints > for clock-names and reset-names. Applied to dt-bindings, thank you! [01/03] dt-bindings: PCI: hisilicon,kirin-pcie: Add top-level constraints https://git.kernel.org/pci/pci/c/ac44be2155cd [02/03] dt-bindings: PCI: renesas,pci-rcar-gen2: Add top-level constraints https://git.kernel.org/pci/pci/c/c62a0b8fe8bf [03/03] dt-bindings: PCI: socionext,uniphier-pcie-ep: Add top-level constraints https://git.kernel.org/pci/pci/c/a5c1bf7e9a46 Krzysztof