Re: [PATCH v15 22/32] ARM: dts: aspeed: yosemite4: Revise i2c duty-cycle

Geert Uytterhoeven
2024-09-06T07:42:15Z

Hi Delphine,

On Fri, Sep 6, 2024 at 8:28 AM Delphine CC Chiu
<Delphine_CC_Chiu@wiwynn.com> wrote:
> Revise duty cycle SMB11 and SMB16 to high: 40%, low: 60%,
> to meet 400kHz-i2c clock low time spec (> 1.3 us) from EE request
>
> Signed-off-by: Delphine CC Chiu <Delphine_CC_Chiu@wiwynn.com>

Thanks for your patch!

> --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
> +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
> @@ -761,6 +761,7 @@ eeprom@54 {
> &i2c10 {
> status = "okay";
> bus-frequency = <400000>;
> + i2c-clk-high-min-percent = <40>;

This property is documented nowhere, except for a not-yet-accepted
patch submission in 2022. It looks like you've been told before, multiple
times...

> i2c-mux@74 {
> compatible = "nxp,pca9544";
> i2c-mux-idle-disconnect;

Gr{oetje,eeting}s,

Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds