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AJvYcCVVYeT3ot0bxVd/3QLev9FlCuk/DWbz06PidJw9ULSyKhsaiylwov0S2kTlVGtgKatcfAWmZF3y0W2/@vger.kernel.org X-Gm-Message-State: AOJu0YwYe4youJq3cEaegBZ3jVj1PbzepHlryxdqZjWqxTG05uAuo7Eb pr5+6Se00nxy9nRXF7A3dyLZTMVFIP7Emwwd9d7FxUiwojMKgrQUG1abEkG5xA== X-Google-Smtp-Source: AGHT+IFcp2jTl5mrKJuFCPH6264r7HZB1RvFjZQoHrVr3k/nmvKN3GCesQlgt2QE0HCgz4564DsufA== X-Received: by 2002:a05:6a21:6481:b0:1cf:539c:56f0 with SMTP id adf61e73a8af0-1d112eaf2eemr4459577637.47.1726234598009; Fri, 13 Sep 2024 06:36:38 -0700 (PDT) Received: from thinkpad ([120.60.66.60]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7190909226fsm6286989b3a.98.2024.09.13.06.36.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Sep 2024 06:36:37 -0700 (PDT) Date: Fri, 13 Sep 2024 19:06:19 +0530 From: Manivannan Sadhasivam To: Dmitry Baryshkov Cc: Qiang Yu , vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, andersson@kernel.org, konradybcio@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, abel.vesa@linaro.org, quic_msarkar@quicinc.com, quic_devipriy@quicinc.com, kw@linux.com, lpieralisi@kernel.org, neil.armstrong@linaro.org, linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org Subject: Re: [PATCH v2 2/5] dt-bindings: PCI: qcom: Add OPP table for X1E80100 Message-ID: <20240913133619.z7cc4whhpvs2uecb@thinkpad> References: <20240913083724.1217691-1-quic_qianyu@quicinc.com> <20240913083724.1217691-3-quic_qianyu@quicinc.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: On Fri, Sep 13, 2024 at 03:30:59PM +0300, Dmitry Baryshkov wrote: > On Fri, Sep 13, 2024 at 01:37:21AM GMT, Qiang Yu wrote: > > Add OPP table so that PCIe is able to adjust power domain performance > > state and ICC peak bw according to PCIe gen speed and link width. > > > > Signed-off-by: Qiang Yu > > --- > > Documentation/devicetree/bindings/pci/qcom,pcie-x1e80100.yaml | 4 ++++ > > 1 file changed, 4 insertions(+) > > > > diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-x1e80100.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-x1e80100.yaml > > index a9db0a231563..e2d6719ca54d 100644 > > --- a/Documentation/devicetree/bindings/pci/qcom,pcie-x1e80100.yaml > > +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-x1e80100.yaml > > @@ -70,6 +70,10 @@ properties: > > - const: pci # PCIe core reset > > - const: link_down # PCIe link down reset > > > > + operating-points-v2: true > > + opp-table: > > + type: object > > I think these properties are generic enough and we might want to have > them for most if not all platforms. Maybe we should move them to > qcom,pcie-common.yaml? > Agree. It should be moved to qcom,pcie-common.yaml. - Mani > Krzysztof, Mani, WDYT? > > > + > > allOf: > > - $ref: qcom,pcie-common.yaml# > > > > -- > > 2.34.1 > > > > > > -- > > linux-phy mailing list > > linux-phy@lists.infradead.org > > https://lists.infradead.org/mailman/listinfo/linux-phy > > -- > With best wishes > Dmitry -- மணிவண்ணன் சதாசிவம்