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Date: Fri, 13 Sep 2024 14:42:10 +0200
From: Greg KH <gregkh@linuxfoundation.org>
To: WangYuli <wangyuli@uniontech.com>
Cc: stable@vger.kernel.org, sashal@kernel.org, william.qiu@starfivetech.com,
	emil.renner.berthing@canonical.com, conor.dooley@microchip.com,
	xingyu.wu@starfivetech.com, walker.chen@starfivetech.com,
	robh@kernel.org, hal.feng@starfivetech.com, kernel@esmil.dk,
	robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org,
	conor+dt@kernel.org, paul.walmsley@sifive.com, palmer@dabbelt.com,
	aou@eecs.berkeley.edu, devicetree@vger.kernel.org,
	linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
	richardcochran@gmail.com, netdev@vger.kernel.org
Subject: Re: [PATCH 6.6 v2 1/4] riscv: dts: starfive: add assigned-clock* to
 limit frquency
Message-ID: <2024091350-lapdog-tarot-0130@gregkh>
References: <3A31C289BC240955+20240912025539.1928223-1-wangyuli@uniontech.com>
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In-Reply-To: <3A31C289BC240955+20240912025539.1928223-1-wangyuli@uniontech.com>

On Thu, Sep 12, 2024 at 10:55:05AM +0800, WangYuli wrote:
> From: William Qiu <william.qiu@starfivetech.com>
> 
> [ Upstream commit af571133f7ae028ec9b5fdab78f483af13bf28d3 ]
> 
> In JH7110 SoC, we need to go by-pass mode, so we need add the
> assigned-clock* properties to limit clock frquency.
> 
> Signed-off-by: William Qiu <william.qiu@starfivetech.com>
> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> Signed-off-by: WangYuli <wangyuli@uniontech.com>
> ---
>  .../riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi | 4 ++++
>  1 file changed, 4 insertions(+)

Please rework this series and send only what is needed here.

thanks,

greg k-h