[PATCH 0/4] clk: lan966x: add support for lan969x SoC clock driver

[PATCH 0/4] clk: lan966x: add support for lan969x SoC clock driver

[Daniel Machon]

Add support for the lan969x SoC clock driver in the existing lan966x
driver. The lan969x clock controller contains 3 PLLs - cpu_clk, ddr_clk
and sys_clk which generates and supplies the clock to various
peripherals within the SoC.

Patch #1 adds compatible strings for lan969x SKU's in the dt-bindings

Patch #2 makes the clk_names var const char * const

Patch #3 prepares the lan966x driver for lan969x, by adding private
         match data.

Patch #4 adds support for lan969x

Signed-off-by: Daniel Machon <daniel.machon@microchip.com>

Signed-off-by: Daniel Machon <daniel.machon@microchip.com>
---
Daniel Machon (4):
      dt-bindings: clock: add support for lan969x
      clk: lan966x: make clk_names const char * const
      clk: lan966x: prepare driver for lan969x support
      clk: lan966x: add support for lan969x SoC clock driver

 .../bindings/clock/microchip,lan966x-gck.yaml      | 13 +++-
 drivers/clk/clk-lan966x.c                          | 79 +++++++++++++++++-----
 2 files changed, 75 insertions(+), 17 deletions(-)
---
base-commit: 3cfb5aa10cb78571e214e48a3a6e42c11d5288a1
change-id: 20240912-lan969x-clock-ac4bc920869c

Best regards,
-- 
Daniel Machon <daniel.machon@microchip.com>

[PATCH 1/4] dt-bindings: clock: add support for lan969x

[Daniel Machon]

Lan969x is going to reuse the existing lan966x clock driver - document
that by adding compatible strings for the different SKU's that we
support.

Signed-off-by: Daniel Machon <daniel.machon@microchip.com>
---
 .../devicetree/bindings/clock/microchip,lan966x-gck.yaml    | 13 ++++++++++++-
 1 file changed, 12 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/clock/microchip,lan966x-gck.yaml b/Documentation/devicetree/bindings/clock/microchip,lan966x-gck.yaml
index df2bec188706..16106e8b637f 100644
--- a/Documentation/devicetree/bindings/clock/microchip,lan966x-gck.yaml
+++ b/Documentation/devicetree/bindings/clock/microchip,lan966x-gck.yaml
@@ -16,7 +16,18 @@ description: |
 
 properties:
   compatible:
-    const: microchip,lan966x-gck
+    oneOf:
+      - enum:
+          - microchip,lan966x-gck
+          - microchip,lan9691-gck
+      - items:
+          - enum:
+              - microchip,lan9698-gck
+              - microchip,lan9696-gck
+              - microchip,lan9694-gck
+              - microchip,lan9693-gck
+              - microchip,lan9692-gck
+          - const: microchip,lan9691-gck
 
   reg:
     minItems: 1

-- 
2.34.1

[PATCH 2/4] clk: lan966x: make clk_names const char * const

[Daniel Machon]

Change clk_names to const char * const to silence checkpatch in
subsequent patches.

Signed-off-by: Daniel Machon <daniel.machon@microchip.com>
---
 drivers/clk/clk-lan966x.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/clk-lan966x.c b/drivers/clk/clk-lan966x.c
index 870fd7df50c1..4dbd4eb0e507 100644
--- a/drivers/clk/clk-lan966x.c
+++ b/drivers/clk/clk-lan966x.c
@@ -24,7 +24,7 @@
 
 #define DIV_MAX		255
 
-static const char *clk_names[N_CLOCKS] = {
+static const char * const clk_names[N_CLOCKS] = {
 	"qspi0", "qspi1", "qspi2", "sdmmc0",
 	"pi", "mcan0", "mcan1", "flexcom0",
 	"flexcom1", "flexcom2", "flexcom3",

-- 
2.34.1

[PATCH 3/4] clk: lan966x: prepare driver for lan969x support

[Daniel Machon]

In preparation for lan969x support, add private match data for lan966x
and add variables for: peripheral clock names, clock gate names, number
of total clocks and number of generic clocks. Use the variables
throughout.

Signed-off-by: Daniel Machon <daniel.machon@microchip.com>
---
 drivers/clk/clk-lan966x.c | 56 +++++++++++++++++++++++++++++++++--------------
 1 file changed, 40 insertions(+), 16 deletions(-)

diff --git a/drivers/clk/clk-lan966x.c b/drivers/clk/clk-lan966x.c
index 4dbd4eb0e507..b25330159446 100644
--- a/drivers/clk/clk-lan966x.c
+++ b/drivers/clk/clk-lan966x.c
@@ -24,7 +24,7 @@
 
 #define DIV_MAX		255
 
-static const char * const clk_names[N_CLOCKS] = {
+static const char * const lan966x_clk_names[] = {
 	"qspi0", "qspi1", "qspi2", "sdmmc0",
 	"pi", "mcan0", "mcan1", "flexcom0",
 	"flexcom1", "flexcom2", "flexcom3",
@@ -53,7 +53,7 @@ struct clk_gate_soc_desc {
 	int bit_idx;
 };
 
-static const struct clk_gate_soc_desc clk_gate_desc[] = {
+static const struct clk_gate_soc_desc lan966x_clk_gate_desc[] = {
 	{ "uhphs", 11 },
 	{ "udphs", 10 },
 	{ "mcramc", 9 },
@@ -61,6 +61,22 @@ static const struct clk_gate_soc_desc clk_gate_desc[] = {
 	{ }
 };
 
+struct lan966x_match_data {
+	char *name;
+	const char * const *clk_name;
+	const struct clk_gate_soc_desc *clk_gate_desc;
+	u8 num_generic_clks;
+	u8 num_total_clks;
+};
+
+static struct lan966x_match_data lan966x_desc = {
+	.name = "lan966x",
+	.clk_name = lan966x_clk_names,
+	.clk_gate_desc = lan966x_clk_gate_desc,
+	.num_total_clks = 18,
+	.num_generic_clks = 14,
+};
+
 static DEFINE_SPINLOCK(clk_gate_lock);
 static void __iomem *base;
 
@@ -186,24 +202,26 @@ static struct clk_hw *lan966x_gck_clk_register(struct device *dev, int i)
 };
 
 static int lan966x_gate_clk_register(struct device *dev,
+				     const struct lan966x_match_data *data,
 				     struct clk_hw_onecell_data *hw_data,
 				     void __iomem *gate_base)
 {
-	int i;
+	for (int i = data->num_generic_clks; i < data->num_total_clks; ++i) {
+		int idx = i - data->num_generic_clks;
+		const struct clk_gate_soc_desc *desc;
 
-	for (i = GCK_GATE_UHPHS; i < N_CLOCKS; ++i) {
-		int idx = i - GCK_GATE_UHPHS;
+		desc = &data->clk_gate_desc[idx];
 
 		hw_data->hws[i] =
-			devm_clk_hw_register_gate(dev, clk_gate_desc[idx].name,
-						  "lan966x", 0, gate_base,
-						  clk_gate_desc[idx].bit_idx,
+			devm_clk_hw_register_gate(dev, desc->name,
+						  data->name, 0, gate_base,
+						  desc->bit_idx,
 						  0, &clk_gate_lock);
 
 		if (IS_ERR(hw_data->hws[i]))
 			return dev_err_probe(dev, PTR_ERR(hw_data->hws[i]),
 					     "failed to register %s clock\n",
-					     clk_gate_desc[idx].name);
+					     desc->name);
 	}
 
 	return 0;
@@ -211,13 +229,19 @@ static int lan966x_gate_clk_register(struct device *dev,
 
 static int lan966x_clk_probe(struct platform_device *pdev)
 {
+	const struct lan966x_match_data *data;
 	struct clk_hw_onecell_data *hw_data;
 	struct device *dev = &pdev->dev;
 	void __iomem *gate_base;
 	struct resource *res;
 	int i, ret;
 
-	hw_data = devm_kzalloc(dev, struct_size(hw_data, hws, N_CLOCKS),
+	data = device_get_match_data(dev);
+	if (!data)
+		return -EINVAL;
+
+	hw_data = devm_kzalloc(dev, struct_size(hw_data, hws,
+						data->num_total_clks),
 			       GFP_KERNEL);
 	if (!hw_data)
 		return -ENOMEM;
@@ -228,10 +252,10 @@ static int lan966x_clk_probe(struct platform_device *pdev)
 
 	init.ops = &lan966x_gck_ops;
 
-	hw_data->num = GCK_GATE_UHPHS;
+	hw_data->num = data->num_generic_clks;
 
-	for (i = 0; i < GCK_GATE_UHPHS; i++) {
-		init.name = clk_names[i];
+	for (i = 0; i < data->num_generic_clks; i++) {
+		init.name = data->clk_name[i];
 		hw_data->hws[i] = lan966x_gck_clk_register(dev, i);
 		if (IS_ERR(hw_data->hws[i])) {
 			dev_err(dev, "failed to register %s clock\n",
@@ -246,9 +270,9 @@ static int lan966x_clk_probe(struct platform_device *pdev)
 		if (IS_ERR(gate_base))
 			return PTR_ERR(gate_base);
 
-		hw_data->num = N_CLOCKS;
+		hw_data->num = data->num_total_clks;
 
-		ret = lan966x_gate_clk_register(dev, hw_data, gate_base);
+		ret = lan966x_gate_clk_register(dev, data, hw_data, gate_base);
 		if (ret)
 			return ret;
 	}
@@ -257,7 +281,7 @@ static int lan966x_clk_probe(struct platform_device *pdev)
 }
 
 static const struct of_device_id lan966x_clk_dt_ids[] = {
-	{ .compatible = "microchip,lan966x-gck", },
+	{ .compatible = "microchip,lan966x-gck", .data = &lan966x_desc },
 	{ }
 };
 MODULE_DEVICE_TABLE(of, lan966x_clk_dt_ids);

-- 
2.34.1

[PATCH 4/4] clk: lan966x: add support for lan969x SoC clock driver

[Daniel Machon]

Add support for the lan969x SoC clock driver in the existing lan966x
driver. The lan969x clock controller contains 3 PLLs - cpu_clk, ddr_clk
and sys_clk (same as lan966x) which generates and supplies the clock to
various peripherals within the SoC.

Signed-off-by: Daniel Machon <daniel.machon@microchip.com>
---
 drivers/clk/clk-lan966x.c | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)

diff --git a/drivers/clk/clk-lan966x.c b/drivers/clk/clk-lan966x.c
index b25330159446..9b928e4a1c62 100644
--- a/drivers/clk/clk-lan966x.c
+++ b/drivers/clk/clk-lan966x.c
@@ -31,6 +31,13 @@ static const char * const lan966x_clk_names[] = {
 	"flexcom4", "timer1", "usb_refclk",
 };
 
+static const char * const lan969x_clk_names[] = {
+	"qspi0", "qspi2", "sdmmc0", "sdmmc1",
+	"mcan0", "mcan1", "flexcom0",
+	"flexcom1", "flexcom2", "flexcom3",
+	"timer1", "usb_refclk",
+};
+
 struct lan966x_gck {
 	struct clk_hw hw;
 	void __iomem *reg;
@@ -61,6 +68,13 @@ static const struct clk_gate_soc_desc lan966x_clk_gate_desc[] = {
 	{ }
 };
 
+static const struct clk_gate_soc_desc lan969x_clk_gate_desc[] = {
+	{ "usb_drd", 10 },
+	{ "mcramc", 9 },
+	{ "hmatrix", 8 },
+	{ }
+};
+
 struct lan966x_match_data {
 	char *name;
 	const char * const *clk_name;
@@ -77,6 +91,14 @@ static struct lan966x_match_data lan966x_desc = {
 	.num_generic_clks = 14,
 };
 
+static struct lan966x_match_data lan969x_desc = {
+	.name = "lan969x",
+	.clk_name = lan969x_clk_names,
+	.clk_gate_desc = lan969x_clk_gate_desc,
+	.num_total_clks = 15,
+	.num_generic_clks = 12,
+};
+
 static DEFINE_SPINLOCK(clk_gate_lock);
 static void __iomem *base;
 
@@ -282,6 +304,7 @@ static int lan966x_clk_probe(struct platform_device *pdev)
 
 static const struct of_device_id lan966x_clk_dt_ids[] = {
 	{ .compatible = "microchip,lan966x-gck", .data = &lan966x_desc },
+	{ .compatible = "microchip,lan9691-gck", .data = &lan969x_desc },
 	{ }
 };
 MODULE_DEVICE_TABLE(of, lan966x_clk_dt_ids);

-- 
2.34.1

Re: [PATCH 1/4] dt-bindings: clock: add support for lan969x

[Conor Dooley]

[-- Attachment #1: Type: text/plain, Size: 1414 bytes --]

On Mon, Sep 16, 2024 at 11:49:19AM +0200, Daniel Machon wrote:
> Lan969x is going to reuse the existing lan966x clock driver - document
> that by adding compatible strings for the different SKU's that we
> support.
> 
> Signed-off-by: Daniel Machon <daniel.machon@microchip.com>

Acked-by: Conor Dooley <conor.dooley@microchip.com>

> ---
>  .../devicetree/bindings/clock/microchip,lan966x-gck.yaml    | 13 ++++++++++++-
>  1 file changed, 12 insertions(+), 1 deletion(-)
> 
> diff --git a/Documentation/devicetree/bindings/clock/microchip,lan966x-gck.yaml b/Documentation/devicetree/bindings/clock/microchip,lan966x-gck.yaml
> index df2bec188706..16106e8b637f 100644
> --- a/Documentation/devicetree/bindings/clock/microchip,lan966x-gck.yaml
> +++ b/Documentation/devicetree/bindings/clock/microchip,lan966x-gck.yaml
> @@ -16,7 +16,18 @@ description: |
>  
>  properties:
>    compatible:
> -    const: microchip,lan966x-gck
> +    oneOf:
> +      - enum:
> +          - microchip,lan966x-gck
> +          - microchip,lan9691-gck
> +      - items:
> +          - enum:
> +              - microchip,lan9698-gck
> +              - microchip,lan9696-gck
> +              - microchip,lan9694-gck
> +              - microchip,lan9693-gck
> +              - microchip,lan9692-gck
> +          - const: microchip,lan9691-gck
>  
>    reg:
>      minItems: 1
> 
> -- 
> 2.34.1
> 

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]

Re: [PATCH 0/4] clk: lan966x: add support for lan969x SoC clock driver

[Stephen Boyd]

Quoting Daniel Machon (2024-09-16 02:49:18)
> Add support for the lan969x SoC clock driver in the existing lan966x
> driver. The lan969x clock controller contains 3 PLLs - cpu_clk, ddr_clk
> and sys_clk which generates and supplies the clock to various
> peripherals within the SoC.
> 
> Patch #1 adds compatible strings for lan969x SKU's in the dt-bindings
> 
> Patch #2 makes the clk_names var const char * const
> 
> Patch #3 prepares the lan966x driver for lan969x, by adding private
>          match data.
> 
> Patch #4 adds support for lan969x
> 
> Signed-off-by: Daniel Machon <daniel.machon@microchip.com>
> 
> Signed-off-by: Daniel Machon <daniel.machon@microchip.com>

Am I supposed to pick up microchip clk patches myself this time?

Re: [PATCH 0/4] clk: lan966x: add support for lan969x SoC clock driver

[claudiu beznea]

On 18.10.2024 01:59, Stephen Boyd wrote:
> Quoting Daniel Machon (2024-09-16 02:49:18)
>> Add support for the lan969x SoC clock driver in the existing lan966x
>> driver. The lan969x clock controller contains 3 PLLs - cpu_clk, ddr_clk
>> and sys_clk which generates and supplies the clock to various
>> peripherals within the SoC.
>>
>> Patch #1 adds compatible strings for lan969x SKU's in the dt-bindings
>>
>> Patch #2 makes the clk_names var const char * const
>>
>> Patch #3 prepares the lan966x driver for lan969x, by adding private
>>          match data.
>>
>> Patch #4 adds support for lan969x
>>
>> Signed-off-by: Daniel Machon <daniel.machon@microchip.com>
>>
>> Signed-off-by: Daniel Machon <daniel.machon@microchip.com>
> 
> Am I supposed to pick up microchip clk patches myself this time?

It's on my track. I already have it on my local queue for a while. Sorry
for not mentioning it yet. I need to run some tests.

Thank you,
Claudiu

> 

Re: [PATCH 0/4] clk: lan966x: add support for lan969x SoC clock driver

[Stephen Boyd]

Quoting claudiu beznea (2024-10-18 01:34:16)
> 
> 
> On 18.10.2024 01:59, Stephen Boyd wrote:
> > Quoting Daniel Machon (2024-09-16 02:49:18)
> >> Add support for the lan969x SoC clock driver in the existing lan966x
> >> driver. The lan969x clock controller contains 3 PLLs - cpu_clk, ddr_clk
> >> and sys_clk which generates and supplies the clock to various
> >> peripherals within the SoC.
> >>
> >> Patch #1 adds compatible strings for lan969x SKU's in the dt-bindings
> >>
> >> Patch #2 makes the clk_names var const char * const
> >>
> >> Patch #3 prepares the lan966x driver for lan969x, by adding private
> >>          match data.
> >>
> >> Patch #4 adds support for lan969x
> >>
> >> Signed-off-by: Daniel Machon <daniel.machon@microchip.com>
> >>
> >> Signed-off-by: Daniel Machon <daniel.machon@microchip.com>
> > 
> > Am I supposed to pick up microchip clk patches myself this time?
> 
> It's on my track. I already have it on my local queue for a while. Sorry
> for not mentioning it yet. I need to run some tests.
> 

Cool. Thanks for taking care of it!

Re: [PATCH 0/4] clk: lan966x: add support for lan969x SoC clock driver

[Claudiu Beznea]

On 16.09.2024 12:49, Daniel Machon wrote:
> Daniel Machon (4):
>       dt-bindings: clock: add support for lan969x
>       clk: lan966x: make clk_names const char * const
>       clk: lan966x: prepare driver for lan969x support
>       clk: lan966x: add support for lan969x SoC clock driver

Applied to clk-microchip, thanks!