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AJvYcCXk1KO7eqj9K7B5RbqtlN+tZIUssHCBs1OVH65BSIWHSmAs64BtMd7hY3WDwB2yon+CYJC6L/1/Y7GB@vger.kernel.org X-Gm-Message-State: AOJu0YwqgHy/bzmohQ3tdkjZGegRn3QjpWKZIGYaC68RAlHapxUwHKr0 cO6J5yNn/DK1RiQ8TwaT5lnP21GaqzKige6VkK+cTWGq2tACpvdGX7OVmygdLg== X-Google-Smtp-Source: AGHT+IEyXFVN8yWlZBr2c0QmUeS9Pixk5O8tibvuF7nDhnrYoQ0QURy2zis3HJYVbJUApjUTxl05fQ== X-Received: by 2002:a17:907:e615:b0:a8d:7046:a1bd with SMTP id a640c23a62f3a-a90d501ad10mr1301633766b.28.1727185822706; Tue, 24 Sep 2024 06:50:22 -0700 (PDT) Received: from thinkpad ([80.66.138.17]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a93931340b5sm85768766b.190.2024.09.24.06.50.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Sep 2024 06:50:22 -0700 (PDT) Date: Tue, 24 Sep 2024 15:50:21 +0200 From: Manivannan Sadhasivam To: Qiang Yu Cc: vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, andersson@kernel.org, konradybcio@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, abel.vesa@linaro.org, quic_msarkar@quicinc.com, quic_devipriy@quicinc.com, dmitry.baryshkov@linaro.org, kw@linux.com, lpieralisi@kernel.org, neil.armstrong@linaro.org, linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org Subject: Re: [PATCH v4 5/6] PCI: qcom: Add support for X1E80100 SoC Message-ID: <20240924135021.ybpyoahlpuvedma5@thinkpad> References: <20240924101444.3933828-1-quic_qianyu@quicinc.com> <20240924101444.3933828-6-quic_qianyu@quicinc.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20240924101444.3933828-6-quic_qianyu@quicinc.com> On Tue, Sep 24, 2024 at 03:14:43AM -0700, Qiang Yu wrote: > X1E80100 has PCIe ports that support up to Gen4 x8 based on hardware IP > version 1.38.0. > > Currently the ops_1_9_0 which is being used for X1E80100 has config_sid > callback to config BDF to SID table. However, this callback is not > required for X1E80100 because it has smmuv3 support and BDF to SID table > will be not present. > > Hence add support for X1E80100 by introducing a new ops and cfg structures > that don't require the config_sid callback. This could be reused by the > future platforms based on SMMUv3. > Oops... I completely overlooked that you are not adding the SoC support but fixing the existing one :( Sorry for suggesting a commit message that changed the context. For this, you can have something like: "PCI: qcom: Fix the ops for X1E80100 SoC X1E80100 SoC is based on SMMUv3, hence it doesn't need the BDF2SID mapping present in the existing cfg_1_9_0 ops. This is fixed by introducing new ops 'ops_1_38_0' and cfg 'cfg_1_38_0' structures. These are exactly same as the 1_9_0 ones, but they don't have the 'config_sid()' callback that handles the BDF2SID mapping in the hardware. These new structures could also be used by the future SoCs making use of SMMUv3." - Mani > Signed-off-by: Qiang Yu > --- > drivers/pci/controller/dwc/pcie-qcom.c | 16 +++++++++++++++- > 1 file changed, 15 insertions(+), 1 deletion(-) > > diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c > index 88a98be930e3..56ba8bc72f78 100644 > --- a/drivers/pci/controller/dwc/pcie-qcom.c > +++ b/drivers/pci/controller/dwc/pcie-qcom.c > @@ -1367,6 +1367,16 @@ static const struct qcom_pcie_ops ops_2_9_0 = { > .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable, > }; > > +/* Qcom IP rev.: 1.38.0 */ > +static const struct qcom_pcie_ops ops_1_38_0 = { > + .get_resources = qcom_pcie_get_resources_2_7_0, > + .init = qcom_pcie_init_2_7_0, > + .post_init = qcom_pcie_post_init_2_7_0, > + .host_post_init = qcom_pcie_host_post_init_2_7_0, > + .deinit = qcom_pcie_deinit_2_7_0, > + .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable, > +}; > + > static const struct qcom_pcie_cfg cfg_1_0_0 = { > .ops = &ops_1_0_0, > }; > @@ -1409,6 +1419,10 @@ static const struct qcom_pcie_cfg cfg_sc8280xp = { > .no_l0s = true, > }; > > +static const struct qcom_pcie_cfg cfg_1_38_0 = { > + .ops = &ops_1_38_0, > +}; > + > static const struct dw_pcie_ops dw_pcie_ops = { > .link_up = qcom_pcie_link_up, > .start_link = qcom_pcie_start_link, > @@ -1837,7 +1851,7 @@ static const struct of_device_id qcom_pcie_match[] = { > { .compatible = "qcom,pcie-sm8450-pcie0", .data = &cfg_1_9_0 }, > { .compatible = "qcom,pcie-sm8450-pcie1", .data = &cfg_1_9_0 }, > { .compatible = "qcom,pcie-sm8550", .data = &cfg_1_9_0 }, > - { .compatible = "qcom,pcie-x1e80100", .data = &cfg_1_9_0 }, > + { .compatible = "qcom,pcie-x1e80100", .data = &cfg_1_38_0 }, > { } > }; > > -- > 2.34.1 > -- மணிவண்ணன் சதாசிவம்