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AJvYcCWpHbD4iqZ8XtyE0MjIfGOoLVjRW3IMfdl68Z3CDWTTwnrX5ofg1rwITFjhxxR/2XDQRvf67kjfPcub@vger.kernel.org X-Gm-Message-State: AOJu0YzNM7p7qzG3kw4hX6E089mnn/+RIuBsDTCfqX9NOQh39lNbb1oq Ua0f4mGegLQfW9vTBpTgYsMtYHEdqM+sYg4krHy4Y3tjCwsO/aquGcnWV3qCwg== X-Google-Smtp-Source: AGHT+IH4WW0ZIOSHklIzJiL/X3r6M9oWzL4NBPDdU5VWxfP/mCN0bTHEJd5jEIb+qLxFYKJld/AuBQ== X-Received: by 2002:a5d:6189:0:b0:371:c518:6f54 with SMTP id ffacd0b85a97d-37a422c02acmr8022006f8f.29.1727186910055; Tue, 24 Sep 2024 07:08:30 -0700 (PDT) Received: from thinkpad ([80.66.138.17]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-37cbc3187e6sm1684265f8f.92.2024.09.24.07.08.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Sep 2024 07:08:29 -0700 (PDT) Date: Tue, 24 Sep 2024 16:08:28 +0200 From: Manivannan Sadhasivam To: Qiang Yu Cc: vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, andersson@kernel.org, konradybcio@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, abel.vesa@linaro.org, quic_msarkar@quicinc.com, quic_devipriy@quicinc.com, dmitry.baryshkov@linaro.org, kw@linux.com, lpieralisi@kernel.org, neil.armstrong@linaro.org, linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org Subject: Re: [PATCH v4 2/6] dt-bindings: PCI: qcom: Move OPP table to qcom,pcie-common.yaml Message-ID: <20240924140828.mz5vjcicygsj4eb4@thinkpad> References: <20240924101444.3933828-1-quic_qianyu@quicinc.com> <20240924101444.3933828-3-quic_qianyu@quicinc.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20240924101444.3933828-3-quic_qianyu@quicinc.com> On Tue, Sep 24, 2024 at 03:14:40AM -0700, Qiang Yu wrote: > OPP table is a generic property that is also required by other qcom > platforms. Hence move this property to qcom,pcie-common.yaml so that PCIe > on other qcom platforms is able to adjust power domain performance state > and ICC peak bw according to PCIe gen speed and link width. > > Signed-off-by: Qiang Yu Reviewed-by: Manivannan Sadhasivam - Mani > --- > Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml | 4 ++++ > Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml | 4 ---- > 2 files changed, 4 insertions(+), 4 deletions(-) > > diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml > index 704c0f58eea5..3c6430fe9331 100644 > --- a/Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml > +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml > @@ -78,6 +78,10 @@ properties: > description: GPIO controlled connection to WAKE# signal > maxItems: 1 > > + operating-points-v2: true > + opp-table: > + type: object > + > required: > - reg > - reg-names > diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml > index 46bd59eefadb..6e0a6d8f0ed0 100644 > --- a/Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml > +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml > @@ -70,10 +70,6 @@ properties: > - const: msi7 > - const: global > > - operating-points-v2: true > - opp-table: > - type: object > - > resets: > maxItems: 1 > > -- > 2.34.1 > -- மணிவண்ணன் சதாசிவம்