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AJvYcCUMPdnn5G2wj18bufgRTpOy0/eEfUl1dCFKMRgEdw8V88HcWwHFPptiCtVeVNo6az9A7gXk76m2DoGV@vger.kernel.org X-Gm-Message-State: AOJu0YxQSCz/4SD1Hn9qXLmf1SXZRTYnCTPrAUyiWyYH6od/+DQgV11G 8kdo6KmafgdE7imhHvVS+7KRUIQgmq82mb8eDBXyolW45KX6CYyUSgr+FWbJ2w== X-Google-Smtp-Source: AGHT+IGu+EQFdqJdQRNdKI2O1nnUzgvF8rHWsav7UIwu3lMA5nKO4ePunuX3F80nTqxwvNWJ8lBRwg== X-Received: by 2002:adf:e7cf:0:b0:374:c64d:5379 with SMTP id ffacd0b85a97d-37cc247945emr1246796f8f.27.1727251523891; Wed, 25 Sep 2024 01:05:23 -0700 (PDT) Received: from thinkpad ([80.66.138.17]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42e90cd8c5asm40971185e9.1.2024.09.25.01.05.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Sep 2024 01:05:23 -0700 (PDT) Date: Wed, 25 Sep 2024 10:05:22 +0200 From: Manivannan Sadhasivam To: Konrad Dybcio Cc: Qiang Yu , vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, andersson@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, abel.vesa@linaro.org, quic_msarkar@quicinc.com, quic_devipriy@quicinc.com, dmitry.baryshkov@linaro.org, kw@linux.com, lpieralisi@kernel.org, neil.armstrong@linaro.org, linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org Subject: Re: [PATCH v4 6/6] arm64: dts: qcom: x1e80100: Add support for PCIe3 on x1e80100 Message-ID: <20240925080522.qwjeyrpjtz64pccx@thinkpad> References: <20240924101444.3933828-1-quic_qianyu@quicinc.com> <20240924101444.3933828-7-quic_qianyu@quicinc.com> <9a692c98-eb0a-4d86-b642-ea655981ff53@kernel.org> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <9a692c98-eb0a-4d86-b642-ea655981ff53@kernel.org> On Tue, Sep 24, 2024 at 04:26:34PM +0200, Konrad Dybcio wrote: > On 24.09.2024 12:14 PM, Qiang Yu wrote: > > Describe PCIe3 controller and PHY. Also add required system resources like > > regulators, clocks, interrupts and registers configuration for PCIe3. > > > > Signed-off-by: Qiang Yu > > Reviewed-by: Dmitry Baryshkov > > --- > > Qiang, Mani > > I have a RTS5261 mmc chip on PCIe3 on the Surface Laptop. Is it based on x1e80100? > Adding the global irq breaks sdcard detection (the chip still comes > up fine) somehow. Removing the irq makes it work again :| > > I've confirmed that the irq number is correct > Yeah, I did see some issues with MSI on SM8250 (RB5) when global interrupts are enabled and I'm working with the hw folks to understand what is going on. But I didn't see the same issues on newer platforms (sa8775p etc...). Can you please confirm if the issue is due to MSI not being received from the device? Checking the /proc/interrutps is enough. - Mani -- மணிவண்ணன் சதாசிவம்