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Lin" , , , , , , , Alexandre Mergnat CC: Bear Wang , Pablo Sun , Macpaul Lin , Sen Chu , "Chris-qj chen" , MediaTek Chromebook Upstream , Chen-Yu Tsai Subject: [PATCH v2 2/5] dt-bindings: iommu: mediatek: Fix interrupt count constraint for new SoCs Date: Thu, 26 Sep 2024 19:14:46 +0800 Message-ID: <20240926111449.9245-2-macpaul.lin@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20240926111449.9245-1-macpaul.lin@mediatek.com> References: <20240926111449.9245-1-macpaul.lin@mediatek.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10-1.215000-8.000000 X-TMASE-MatchedRID: P0y1Pz0bU7nwBTQ+XvV6VYzb2GR6Ttd3MZm0+sEE9msY0A95tjAn+9EQ LJPlYQqE0KHDXPxFjpD1VmTZnVKT+CaIC0lz+Wv3rQcmzcV8ovxbAoaK+wS4jUS/boWSGMtdi3N TyIt6V8peAwsJFuYQ4wTqbINU49IGbC1/2cudIH8SS5pQAyYxiqAPS3vFyaW6SSUXkvSVAdxZoZ UwtnkREuLzNWBegCW2wgn7iDBesS0qyYS0oyUVZrz092AhSRMerXqvQ7Xsx4NYyfd5fyfN9NdvP HFMK5cWUMepMtjA+idw3nV6gQuaZHRLk7foSK6ptbu7GfNV+t87DHWNfN2q6oSVUZZHNLr+RgV6 Hsqyx11QaONuZ6Jr4g9k3l8EaYIcOQLK/ZH4rlaeqD9WtJkSIw== X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10-1.215000-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: 3C0E2BE1189122A4A3757AF41D63E367D739BF21E4BD2B17129FB16398AB53EB2000:8 X-MTK: N The infra-iommu node in mt8195.dtsi was triggering a CHECK_DTBS error due to an excessively long 'interrupts' property. The error message was: infra-iommu@10315000: interrupts: [[0, 795, 4, 0], [0, 796, 4, 0], [0, 797, 4, 0], [0, 798, 4, 0], [0, 799, 4, 0]] is too long To address this issue, add "minItems: 1" and "maxItems: 5" constraints to the 'interrupts' property in the DT binding schema. This change allows for flexibility in the number of interrupts for new SoCs. The purpose of these 5 interrupts is also added. Fixes: bca28426805d ("dt-bindings: iommu: mediatek: Convert IOMMU to DT schema") Signed-off-by: Macpaul Lin --- .../bindings/iommu/mediatek,iommu.yaml | 25 ++++++++++++++++++- 1 file changed, 24 insertions(+), 1 deletion(-) Changes for v2: - commit message: re-formatting and add a description of adding 5 interrupts. - add 'description' and 'maxItems: 5' for 'interrupt' property of 'mt8195-iommu-infra' - others keeps 'maxItems: 1' diff --git a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml index ea6b0f5f24de..fdd2996d2a31 100644 --- a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml +++ b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml @@ -96,7 +96,8 @@ properties: maxItems: 1 interrupts: - maxItems: 1 + minItems: 1 + maxItems: 5 clocks: items: @@ -210,6 +211,28 @@ allOf: required: - mediatek,larbs + - if: + properties: + compatible: + contains: + enum: + - mediatek,mt8195-iommu-infra + + then: + properties: + interrupts: + description: | + The IOMMU of MT8195 has 5 banks: 0/1/2/3/4. + Each bank has a set of APB registers corresponding to the + normal world, protected world 1/2/3, and secure world, respectively. + Therefore, 5 interrupt numbers are needed. + maxItems: 5 + + else: + properties: + interrupts: + maxItems: 1 + additionalProperties: false examples: -- 2.45.2