* [PATCH 0/3] pinctrl: s32: add missing pins and an S32G3 compatible
@ 2024-09-30 13:23 Andrei Stefanescu
2024-09-30 13:23 ` [PATCH 1/3] pinctrl: s32: add missing pins definitions Andrei Stefanescu
` (2 more replies)
0 siblings, 3 replies; 9+ messages in thread
From: Andrei Stefanescu @ 2024-09-30 13:23 UTC (permalink / raw)
To: Dong Aisheng, Fabio Estevam, Shawn Guo, Jacky Bai, Linus Walleij,
Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Ghennadi Procopciuc, Chester Lin, Matthias Brugger, Sascha Hauer
Cc: Pengutronix Kernel Team, linux-gpio, devicetree, linux-kernel,
linux-arm-kernel, imx, NXP S32 Linux Team, Christophe Lizzi,
Alberto Ruiz, Enric Balletbo, Andrei Stefanescu
This patch series adds some small fixes to the SIUL2 pinctrl driver:
- Add some missing pin definitions.
- Add another S32G3 compatible and use it in the s32g3.dtsi file.
It will fall back to the S32G2 compatible.
Andrei Stefanescu (3):
pinctrl: s32: add missing pins definitions
dt-bindings: pinctrl: add S32G3 compatible for the SIUL2 driver
arm64: dts: S32G3: add S32G3 compatible for the pinctrl node
.../pinctrl/nxp,s32g2-siul2-pinctrl.yaml | 10 +++-
arch/arm64/boot/dts/freescale/s32g3.dtsi | 3 +-
drivers/pinctrl/nxp/pinctrl-s32g2.c | 52 +++++++++++++++++++
3 files changed, 62 insertions(+), 3 deletions(-)
--
2.45.2
^ permalink raw reply [flat|nested] 9+ messages in thread* [PATCH 1/3] pinctrl: s32: add missing pins definitions 2024-09-30 13:23 [PATCH 0/3] pinctrl: s32: add missing pins and an S32G3 compatible Andrei Stefanescu @ 2024-09-30 13:23 ` Andrei Stefanescu 2024-10-02 11:58 ` Matthias Brugger 2024-09-30 13:23 ` [PATCH 2/3] dt-bindings: pinctrl: add S32G3 compatible for the SIUL2 driver Andrei Stefanescu 2024-09-30 13:23 ` [PATCH 3/3] arm64: dts: S32G3: add S32G3 compatible for the pinctrl node Andrei Stefanescu 2 siblings, 1 reply; 9+ messages in thread From: Andrei Stefanescu @ 2024-09-30 13:23 UTC (permalink / raw) To: Dong Aisheng, Fabio Estevam, Shawn Guo, Jacky Bai, Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Ghennadi Procopciuc, Chester Lin, Matthias Brugger, Sascha Hauer Cc: Pengutronix Kernel Team, linux-gpio, devicetree, linux-kernel, linux-arm-kernel, imx, NXP S32 Linux Team, Christophe Lizzi, Alberto Ruiz, Enric Balletbo, Andrei Stefanescu Added definitions for some pins which were missing from the S32G2 SIUL2 pinctrl driver. These pins are used by the JTAG, PFE and LLCE hardware modules. Signed-off-by: Andrei Stefanescu <andrei.stefanescu@oss.nxp.com> --- drivers/pinctrl/nxp/pinctrl-s32g2.c | 52 +++++++++++++++++++++++++++++ 1 file changed, 52 insertions(+) diff --git a/drivers/pinctrl/nxp/pinctrl-s32g2.c b/drivers/pinctrl/nxp/pinctrl-s32g2.c index 440ff1879424..c49d28793b69 100644 --- a/drivers/pinctrl/nxp/pinctrl-s32g2.c +++ b/drivers/pinctrl/nxp/pinctrl-s32g2.c @@ -216,6 +216,12 @@ enum s32_pins { S32G_IMCR_CAN1_RXD = 631, S32G_IMCR_CAN2_RXD = 632, S32G_IMCR_CAN3_RXD = 633, + + /* JTAG IMCRs */ + S32G_IMCR_JTAG_TMS = 562, + S32G_IMCR_JTAG_TCK = 572, + S32G_IMCR_JTAG_TDI = 573, + /* GMAC0 */ S32G_IMCR_Ethernet_MDIO = 527, S32G_IMCR_Ethernet_CRS = 526, @@ -229,7 +235,21 @@ enum s32_pins { S32G_IMCR_Ethernet_RX_DV = 530, S32G_IMCR_Ethernet_TX_CLK = 538, S32G_IMCR_Ethernet_REF_CLK = 535, + /* PFE EMAC 0 MII */ + S32G_IMCR_PFE_EMAC_0_MDIO = 837, + S32G_IMCR_PFE_EMAC_0_CRS = 836, + S32G_IMCR_PFE_EMAC_0_COL = 835, + S32G_IMCR_PFE_EMAC_0_RX_D0 = 841, + S32G_IMCR_PFE_EMAC_0_RX_D1 = 842, + S32G_IMCR_PFE_EMAC_0_RX_D2 = 843, + S32G_IMCR_PFE_EMAC_0_RX_D3 = 844, + S32G_IMCR_PFE_EMAC_0_RX_ER = 840, + S32G_IMCR_PFE_EMAC_0_RX_CLK = 839, + S32G_IMCR_PFE_EMAC_0_RX_DV = 845, + S32G_IMCR_PFE_EMAC_0_TX_CLK = 846, + S32G_IMCR_PFE_EMAC_0_REF_CLK = 838, + /* PFE EMAC 1 MII */ S32G_IMCR_PFE_EMAC_1_MDIO = 857, S32G_IMCR_PFE_EMAC_1_CRS = 856, @@ -317,6 +337,13 @@ enum s32_pins { S32G_IMCR_LLCE_CAN13_RXD = 758, S32G_IMCR_LLCE_CAN14_RXD = 759, S32G_IMCR_LLCE_CAN15_RXD = 760, + S32G_IMCR_LLCE_UART0_RXD = 790, + S32G_IMCR_LLCE_UART1_RXD = 791, + S32G_IMCR_LLCE_UART2_RXD = 792, + S32G_IMCR_LLCE_UART3_RXD = 793, + S32G_IMCR_LLCE_LPSPI2_PCS0 = 811, + S32G_IMCR_LLCE_LPSPI2_SCK = 816, + S32G_IMCR_LLCE_LPSPI2_SIN = 817, S32G_IMCR_USB_CLK = 895, S32G_IMCR_USB_DATA0 = 896, S32G_IMCR_USB_DATA1 = 897, @@ -503,6 +530,12 @@ static const struct pinctrl_pin_desc s32_pinctrl_pads_siul2[] = { S32_PINCTRL_PIN(S32G_IMCR_USDHC_DAT7), S32_PINCTRL_PIN(S32G_IMCR_USDHC_DQS), S32_PINCTRL_PIN(S32G_IMCR_CAN0_RXD), + + /* JTAG IMCRs */ + S32_PINCTRL_PIN(S32G_IMCR_JTAG_TMS), + S32_PINCTRL_PIN(S32G_IMCR_JTAG_TCK), + S32_PINCTRL_PIN(S32G_IMCR_JTAG_TDI), + /* GMAC0 */ S32_PINCTRL_PIN(S32G_IMCR_Ethernet_MDIO), S32_PINCTRL_PIN(S32G_IMCR_Ethernet_CRS), @@ -638,6 +671,13 @@ static const struct pinctrl_pin_desc s32_pinctrl_pads_siul2[] = { S32_PINCTRL_PIN(S32G_IMCR_LLCE_CAN13_RXD), S32_PINCTRL_PIN(S32G_IMCR_LLCE_CAN14_RXD), S32_PINCTRL_PIN(S32G_IMCR_LLCE_CAN15_RXD), + S32_PINCTRL_PIN(S32G_IMCR_LLCE_UART0_RXD), + S32_PINCTRL_PIN(S32G_IMCR_LLCE_UART1_RXD), + S32_PINCTRL_PIN(S32G_IMCR_LLCE_UART2_RXD), + S32_PINCTRL_PIN(S32G_IMCR_LLCE_UART3_RXD), + S32_PINCTRL_PIN(S32G_IMCR_LLCE_LPSPI2_PCS0), + S32_PINCTRL_PIN(S32G_IMCR_LLCE_LPSPI2_SCK), + S32_PINCTRL_PIN(S32G_IMCR_LLCE_LPSPI2_SIN), S32_PINCTRL_PIN(S32G_IMCR_CAN1_RXD), S32_PINCTRL_PIN(S32G_IMCR_CAN2_RXD), S32_PINCTRL_PIN(S32G_IMCR_CAN3_RXD), @@ -652,6 +692,18 @@ static const struct pinctrl_pin_desc s32_pinctrl_pads_siul2[] = { S32_PINCTRL_PIN(S32G_IMCR_USB_DATA7), S32_PINCTRL_PIN(S32G_IMCR_USB_DIR), S32_PINCTRL_PIN(S32G_IMCR_USB_NXT), + S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_0_MDIO), + S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_0_CRS), + S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_0_COL), + S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_0_RX_D0), + S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_0_RX_D1), + S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_0_RX_D2), + S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_0_RX_D3), + S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_0_RX_ER), + S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_0_RX_CLK), + S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_0_RX_DV), + S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_0_TX_CLK), + S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_0_REF_CLK), S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_1_MDIO), S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_1_CRS), S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_1_COL), -- 2.45.2 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH 1/3] pinctrl: s32: add missing pins definitions 2024-09-30 13:23 ` [PATCH 1/3] pinctrl: s32: add missing pins definitions Andrei Stefanescu @ 2024-10-02 11:58 ` Matthias Brugger 0 siblings, 0 replies; 9+ messages in thread From: Matthias Brugger @ 2024-10-02 11:58 UTC (permalink / raw) To: Andrei Stefanescu, Dong Aisheng, Fabio Estevam, Shawn Guo, Jacky Bai, Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Ghennadi Procopciuc, Chester Lin, Sascha Hauer Cc: Pengutronix Kernel Team, linux-gpio, devicetree, linux-kernel, linux-arm-kernel, imx, NXP S32 Linux Team, Christophe Lizzi, Alberto Ruiz, Enric Balletbo On 30/09/2024 15:23, Andrei Stefanescu wrote: > Added definitions for some pins which were missing from the > S32G2 SIUL2 pinctrl driver. These pins are used by the JTAG, > PFE and LLCE hardware modules. > > Signed-off-by: Andrei Stefanescu <andrei.stefanescu@oss.nxp.com> Reviewed-by: Matthias Brugger <mbrugger@suse.com> > --- > drivers/pinctrl/nxp/pinctrl-s32g2.c | 52 +++++++++++++++++++++++++++++ > 1 file changed, 52 insertions(+) > > diff --git a/drivers/pinctrl/nxp/pinctrl-s32g2.c b/drivers/pinctrl/nxp/pinctrl-s32g2.c > index 440ff1879424..c49d28793b69 100644 > --- a/drivers/pinctrl/nxp/pinctrl-s32g2.c > +++ b/drivers/pinctrl/nxp/pinctrl-s32g2.c > @@ -216,6 +216,12 @@ enum s32_pins { > S32G_IMCR_CAN1_RXD = 631, > S32G_IMCR_CAN2_RXD = 632, > S32G_IMCR_CAN3_RXD = 633, > + > + /* JTAG IMCRs */ > + S32G_IMCR_JTAG_TMS = 562, > + S32G_IMCR_JTAG_TCK = 572, > + S32G_IMCR_JTAG_TDI = 573, > + > /* GMAC0 */ > S32G_IMCR_Ethernet_MDIO = 527, > S32G_IMCR_Ethernet_CRS = 526, > @@ -229,7 +235,21 @@ enum s32_pins { > S32G_IMCR_Ethernet_RX_DV = 530, > S32G_IMCR_Ethernet_TX_CLK = 538, > S32G_IMCR_Ethernet_REF_CLK = 535, > + > /* PFE EMAC 0 MII */ > + S32G_IMCR_PFE_EMAC_0_MDIO = 837, > + S32G_IMCR_PFE_EMAC_0_CRS = 836, > + S32G_IMCR_PFE_EMAC_0_COL = 835, > + S32G_IMCR_PFE_EMAC_0_RX_D0 = 841, > + S32G_IMCR_PFE_EMAC_0_RX_D1 = 842, > + S32G_IMCR_PFE_EMAC_0_RX_D2 = 843, > + S32G_IMCR_PFE_EMAC_0_RX_D3 = 844, > + S32G_IMCR_PFE_EMAC_0_RX_ER = 840, > + S32G_IMCR_PFE_EMAC_0_RX_CLK = 839, > + S32G_IMCR_PFE_EMAC_0_RX_DV = 845, > + S32G_IMCR_PFE_EMAC_0_TX_CLK = 846, > + S32G_IMCR_PFE_EMAC_0_REF_CLK = 838, > + > /* PFE EMAC 1 MII */ > S32G_IMCR_PFE_EMAC_1_MDIO = 857, > S32G_IMCR_PFE_EMAC_1_CRS = 856, > @@ -317,6 +337,13 @@ enum s32_pins { > S32G_IMCR_LLCE_CAN13_RXD = 758, > S32G_IMCR_LLCE_CAN14_RXD = 759, > S32G_IMCR_LLCE_CAN15_RXD = 760, > + S32G_IMCR_LLCE_UART0_RXD = 790, > + S32G_IMCR_LLCE_UART1_RXD = 791, > + S32G_IMCR_LLCE_UART2_RXD = 792, > + S32G_IMCR_LLCE_UART3_RXD = 793, > + S32G_IMCR_LLCE_LPSPI2_PCS0 = 811, > + S32G_IMCR_LLCE_LPSPI2_SCK = 816, > + S32G_IMCR_LLCE_LPSPI2_SIN = 817, > S32G_IMCR_USB_CLK = 895, > S32G_IMCR_USB_DATA0 = 896, > S32G_IMCR_USB_DATA1 = 897, > @@ -503,6 +530,12 @@ static const struct pinctrl_pin_desc s32_pinctrl_pads_siul2[] = { > S32_PINCTRL_PIN(S32G_IMCR_USDHC_DAT7), > S32_PINCTRL_PIN(S32G_IMCR_USDHC_DQS), > S32_PINCTRL_PIN(S32G_IMCR_CAN0_RXD), > + > + /* JTAG IMCRs */ > + S32_PINCTRL_PIN(S32G_IMCR_JTAG_TMS), > + S32_PINCTRL_PIN(S32G_IMCR_JTAG_TCK), > + S32_PINCTRL_PIN(S32G_IMCR_JTAG_TDI), > + > /* GMAC0 */ > S32_PINCTRL_PIN(S32G_IMCR_Ethernet_MDIO), > S32_PINCTRL_PIN(S32G_IMCR_Ethernet_CRS), > @@ -638,6 +671,13 @@ static const struct pinctrl_pin_desc s32_pinctrl_pads_siul2[] = { > S32_PINCTRL_PIN(S32G_IMCR_LLCE_CAN13_RXD), > S32_PINCTRL_PIN(S32G_IMCR_LLCE_CAN14_RXD), > S32_PINCTRL_PIN(S32G_IMCR_LLCE_CAN15_RXD), > + S32_PINCTRL_PIN(S32G_IMCR_LLCE_UART0_RXD), > + S32_PINCTRL_PIN(S32G_IMCR_LLCE_UART1_RXD), > + S32_PINCTRL_PIN(S32G_IMCR_LLCE_UART2_RXD), > + S32_PINCTRL_PIN(S32G_IMCR_LLCE_UART3_RXD), > + S32_PINCTRL_PIN(S32G_IMCR_LLCE_LPSPI2_PCS0), > + S32_PINCTRL_PIN(S32G_IMCR_LLCE_LPSPI2_SCK), > + S32_PINCTRL_PIN(S32G_IMCR_LLCE_LPSPI2_SIN), > S32_PINCTRL_PIN(S32G_IMCR_CAN1_RXD), > S32_PINCTRL_PIN(S32G_IMCR_CAN2_RXD), > S32_PINCTRL_PIN(S32G_IMCR_CAN3_RXD), > @@ -652,6 +692,18 @@ static const struct pinctrl_pin_desc s32_pinctrl_pads_siul2[] = { > S32_PINCTRL_PIN(S32G_IMCR_USB_DATA7), > S32_PINCTRL_PIN(S32G_IMCR_USB_DIR), > S32_PINCTRL_PIN(S32G_IMCR_USB_NXT), > + S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_0_MDIO), > + S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_0_CRS), > + S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_0_COL), > + S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_0_RX_D0), > + S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_0_RX_D1), > + S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_0_RX_D2), > + S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_0_RX_D3), > + S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_0_RX_ER), > + S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_0_RX_CLK), > + S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_0_RX_DV), > + S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_0_TX_CLK), > + S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_0_REF_CLK), > S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_1_MDIO), > S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_1_CRS), > S32_PINCTRL_PIN(S32G_IMCR_PFE_EMAC_1_COL), ^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 2/3] dt-bindings: pinctrl: add S32G3 compatible for the SIUL2 driver 2024-09-30 13:23 [PATCH 0/3] pinctrl: s32: add missing pins and an S32G3 compatible Andrei Stefanescu 2024-09-30 13:23 ` [PATCH 1/3] pinctrl: s32: add missing pins definitions Andrei Stefanescu @ 2024-09-30 13:23 ` Andrei Stefanescu 2024-09-30 13:40 ` Krzysztof Kozlowski 2024-09-30 13:23 ` [PATCH 3/3] arm64: dts: S32G3: add S32G3 compatible for the pinctrl node Andrei Stefanescu 2 siblings, 1 reply; 9+ messages in thread From: Andrei Stefanescu @ 2024-09-30 13:23 UTC (permalink / raw) To: Dong Aisheng, Fabio Estevam, Shawn Guo, Jacky Bai, Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Ghennadi Procopciuc, Chester Lin, Matthias Brugger, Sascha Hauer Cc: Pengutronix Kernel Team, linux-gpio, devicetree, linux-kernel, linux-arm-kernel, imx, NXP S32 Linux Team, Christophe Lizzi, Alberto Ruiz, Enric Balletbo, Andrei Stefanescu The SIUL2 hardware module is also integrated into the S32G3 SoC. Add another compatible for it. Signed-off-by: Andrei Stefanescu <andrei.stefanescu@oss.nxp.com> --- .../bindings/pinctrl/nxp,s32g2-siul2-pinctrl.yaml | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/nxp,s32g2-siul2-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/nxp,s32g2-siul2-pinctrl.yaml index a24286e4def6..454773e7aa07 100644 --- a/Documentation/devicetree/bindings/pinctrl/nxp,s32g2-siul2-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/nxp,s32g2-siul2-pinctrl.yaml @@ -25,8 +25,14 @@ description: | properties: compatible: - enum: - - nxp,s32g2-siul2-pinctrl + oneOf: + - description: for S32G2 SoCs + items: + - const: nxp,s32g2-siul2-pinctrl + - description: for S32G3 SoCs + items: + - const: nxp,s32g3-siul2-pinctrl + - const: nxp,s32g2-siul2-pinctrl reg: description: | -- 2.45.2 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH 2/3] dt-bindings: pinctrl: add S32G3 compatible for the SIUL2 driver 2024-09-30 13:23 ` [PATCH 2/3] dt-bindings: pinctrl: add S32G3 compatible for the SIUL2 driver Andrei Stefanescu @ 2024-09-30 13:40 ` Krzysztof Kozlowski 2024-09-30 14:46 ` Andrei Stefanescu 0 siblings, 1 reply; 9+ messages in thread From: Krzysztof Kozlowski @ 2024-09-30 13:40 UTC (permalink / raw) To: Andrei Stefanescu, Dong Aisheng, Fabio Estevam, Shawn Guo, Jacky Bai, Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Ghennadi Procopciuc, Chester Lin, Matthias Brugger, Sascha Hauer Cc: Pengutronix Kernel Team, linux-gpio, devicetree, linux-kernel, linux-arm-kernel, imx, NXP S32 Linux Team, Christophe Lizzi, Alberto Ruiz, Enric Balletbo On 30/09/2024 15:23, Andrei Stefanescu wrote: > The SIUL2 hardware module is also integrated into the S32G3 SoC. Add > another compatible for it. > > Signed-off-by: Andrei Stefanescu <andrei.stefanescu@oss.nxp.com> > --- > .../bindings/pinctrl/nxp,s32g2-siul2-pinctrl.yaml | 10 ++++++++-- > 1 file changed, 8 insertions(+), 2 deletions(-) > > diff --git a/Documentation/devicetree/bindings/pinctrl/nxp,s32g2-siul2-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/nxp,s32g2-siul2-pinctrl.yaml > index a24286e4def6..454773e7aa07 100644 > --- a/Documentation/devicetree/bindings/pinctrl/nxp,s32g2-siul2-pinctrl.yaml > +++ b/Documentation/devicetree/bindings/pinctrl/nxp,s32g2-siul2-pinctrl.yaml > @@ -25,8 +25,14 @@ description: | > > properties: > compatible: > - enum: > - - nxp,s32g2-siul2-pinctrl > + oneOf: > + - description: for S32G2 SoCs Drop > + items: That's jus tenum > + - const: nxp,s32g2-siul2-pinctrl Drop > + - description: for S32G3 SoCs > + items: Best regards, Krzysztof ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 2/3] dt-bindings: pinctrl: add S32G3 compatible for the SIUL2 driver 2024-09-30 13:40 ` Krzysztof Kozlowski @ 2024-09-30 14:46 ` Andrei Stefanescu 2024-10-01 6:20 ` Krzysztof Kozlowski 0 siblings, 1 reply; 9+ messages in thread From: Andrei Stefanescu @ 2024-09-30 14:46 UTC (permalink / raw) To: Krzysztof Kozlowski, Dong Aisheng, Fabio Estevam, Shawn Guo, Jacky Bai, Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Ghennadi Procopciuc, Chester Lin, Matthias Brugger, Sascha Hauer Cc: Pengutronix Kernel Team, linux-gpio, devicetree, linux-kernel, linux-arm-kernel, imx, NXP S32 Linux Team, Christophe Lizzi, Alberto Ruiz, Enric Balletbo Hi Krzysztof, Thank you for the quick review! On 30/09/2024 16:40, Krzysztof Kozlowski wrote: > On 30/09/2024 15:23, Andrei Stefanescu wrote: >> The SIUL2 hardware module is also integrated into the S32G3 SoC. Add >> another compatible for it. >> >> Signed-off-by: Andrei Stefanescu <andrei.stefanescu@oss.nxp.com> >> --- >> .../bindings/pinctrl/nxp,s32g2-siul2-pinctrl.yaml | 10 ++++++++-- >> 1 file changed, 8 insertions(+), 2 deletions(-) >> >> diff --git a/Documentation/devicetree/bindings/pinctrl/nxp,s32g2-siul2-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/nxp,s32g2-siul2-pinctrl.yaml >> index a24286e4def6..454773e7aa07 100644 >> --- a/Documentation/devicetree/bindings/pinctrl/nxp,s32g2-siul2-pinctrl.yaml >> +++ b/Documentation/devicetree/bindings/pinctrl/nxp,s32g2-siul2-pinctrl.yaml >> @@ -25,8 +25,14 @@ description: | >> >> properties: >> compatible: >> - enum: >> - - nxp,s32g2-siul2-pinctrl >> + oneOf: >> + - description: for S32G2 SoCs > > Drop > >> + items: > > That's jus tenum > >> + - const: nxp,s32g2-siul2-pinctrl > > Drop > >> + - description: for S32G3 SoCs >> + items: Just to make sure I understood correctly, it should look something like this, right? oneOf: - enum: - const: nxp,s32g2-siul2-pinctrl - items: - const: nxp,s32g3-siul2-pinctrl - const: nxp,s32g2-siul2-pinctrl > Best regards, > Krzysztof > Best regards, Andrei ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 2/3] dt-bindings: pinctrl: add S32G3 compatible for the SIUL2 driver 2024-09-30 14:46 ` Andrei Stefanescu @ 2024-10-01 6:20 ` Krzysztof Kozlowski 0 siblings, 0 replies; 9+ messages in thread From: Krzysztof Kozlowski @ 2024-10-01 6:20 UTC (permalink / raw) To: Andrei Stefanescu, Dong Aisheng, Fabio Estevam, Shawn Guo, Jacky Bai, Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Ghennadi Procopciuc, Chester Lin, Matthias Brugger, Sascha Hauer Cc: Pengutronix Kernel Team, linux-gpio, devicetree, linux-kernel, linux-arm-kernel, imx, NXP S32 Linux Team, Christophe Lizzi, Alberto Ruiz, Enric Balletbo On 30/09/2024 16:46, Andrei Stefanescu wrote: > > Just to make sure I understood correctly, it should > look something like this, right? > > oneOf: > - enum: > - const: nxp,s32g2-siul2-pinctrl > - items: > - const: nxp,s32g3-siul2-pinctrl > - const: nxp,s32g2-siul2-pinctrl Yes. Just like we do in other files... Best regards, Krzysztof ^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 3/3] arm64: dts: S32G3: add S32G3 compatible for the pinctrl node 2024-09-30 13:23 [PATCH 0/3] pinctrl: s32: add missing pins and an S32G3 compatible Andrei Stefanescu 2024-09-30 13:23 ` [PATCH 1/3] pinctrl: s32: add missing pins definitions Andrei Stefanescu 2024-09-30 13:23 ` [PATCH 2/3] dt-bindings: pinctrl: add S32G3 compatible for the SIUL2 driver Andrei Stefanescu @ 2024-09-30 13:23 ` Andrei Stefanescu 2024-10-02 12:00 ` Matthias Brugger 2 siblings, 1 reply; 9+ messages in thread From: Andrei Stefanescu @ 2024-09-30 13:23 UTC (permalink / raw) To: Dong Aisheng, Fabio Estevam, Shawn Guo, Jacky Bai, Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Ghennadi Procopciuc, Chester Lin, Matthias Brugger, Sascha Hauer Cc: Pengutronix Kernel Team, linux-gpio, devicetree, linux-kernel, linux-arm-kernel, imx, NXP S32 Linux Team, Christophe Lizzi, Alberto Ruiz, Enric Balletbo, Andrei Stefanescu Add the newly introduced S32G3 compatible for the pinctrl node. Currently, it will fall back to the S32G2 compatible. Signed-off-by: Andrei Stefanescu <andrei.stefanescu@oss.nxp.com> --- arch/arm64/boot/dts/freescale/s32g3.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts/freescale/s32g3.dtsi index b4226a9143c8..f6aafe44c9d7 100644 --- a/arch/arm64/boot/dts/freescale/s32g3.dtsi +++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi @@ -172,7 +172,8 @@ soc@0 { ranges = <0 0 0 0x80000000>; pinctrl: pinctrl@4009c240 { - compatible = "nxp,s32g2-siul2-pinctrl"; + compatible = "nxp,s32g3-siul2-pinctrl", + "nxp,s32g2-siul2-pinctrl"; /* MSCR0-MSCR101 registers on siul2_0 */ reg = <0x4009c240 0x198>, /* MSCR112-MSCR122 registers on siul2_1 */ -- 2.45.2 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH 3/3] arm64: dts: S32G3: add S32G3 compatible for the pinctrl node 2024-09-30 13:23 ` [PATCH 3/3] arm64: dts: S32G3: add S32G3 compatible for the pinctrl node Andrei Stefanescu @ 2024-10-02 12:00 ` Matthias Brugger 0 siblings, 0 replies; 9+ messages in thread From: Matthias Brugger @ 2024-10-02 12:00 UTC (permalink / raw) To: Andrei Stefanescu, Dong Aisheng, Fabio Estevam, Shawn Guo, Jacky Bai, Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Ghennadi Procopciuc, Chester Lin, Sascha Hauer Cc: Pengutronix Kernel Team, linux-gpio, devicetree, linux-kernel, linux-arm-kernel, imx, NXP S32 Linux Team, Christophe Lizzi, Alberto Ruiz, Enric Balletbo On 30/09/2024 15:23, Andrei Stefanescu wrote: > Add the newly introduced S32G3 compatible for the pinctrl node. > Currently, it will fall back to the S32G2 compatible. > > Signed-off-by: Andrei Stefanescu <andrei.stefanescu@oss.nxp.com> Reviewed-by: Matthias Brugger <mbrugger@suse.com> > --- > arch/arm64/boot/dts/freescale/s32g3.dtsi | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts/freescale/s32g3.dtsi > index b4226a9143c8..f6aafe44c9d7 100644 > --- a/arch/arm64/boot/dts/freescale/s32g3.dtsi > +++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi > @@ -172,7 +172,8 @@ soc@0 { > ranges = <0 0 0 0x80000000>; > > pinctrl: pinctrl@4009c240 { > - compatible = "nxp,s32g2-siul2-pinctrl"; > + compatible = "nxp,s32g3-siul2-pinctrl", > + "nxp,s32g2-siul2-pinctrl"; > /* MSCR0-MSCR101 registers on siul2_0 */ > reg = <0x4009c240 0x198>, > /* MSCR112-MSCR122 registers on siul2_1 */ ^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2024-10-02 12:00 UTC | newest] Thread overview: 9+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2024-09-30 13:23 [PATCH 0/3] pinctrl: s32: add missing pins and an S32G3 compatible Andrei Stefanescu 2024-09-30 13:23 ` [PATCH 1/3] pinctrl: s32: add missing pins definitions Andrei Stefanescu 2024-10-02 11:58 ` Matthias Brugger 2024-09-30 13:23 ` [PATCH 2/3] dt-bindings: pinctrl: add S32G3 compatible for the SIUL2 driver Andrei Stefanescu 2024-09-30 13:40 ` Krzysztof Kozlowski 2024-09-30 14:46 ` Andrei Stefanescu 2024-10-01 6:20 ` Krzysztof Kozlowski 2024-09-30 13:23 ` [PATCH 3/3] arm64: dts: S32G3: add S32G3 compatible for the pinctrl node Andrei Stefanescu 2024-10-02 12:00 ` Matthias Brugger
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