From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pf1-f172.google.com (mail-pf1-f172.google.com [209.85.210.172]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0447C201268 for ; Wed, 2 Oct 2024 11:46:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727869621; cv=none; b=ek78KsBZrCIz2H7OuYzbWa4zzFyk83Suuvq2cQMAXd4+UPdhuiyLQiWz11tEIQmOSY77JVeKB1Xl7cTwIb+jqZs3lmhz10MWLi8HSDDXuBZnmUQlKkEoJ3Kb3V6TuEhI4t5XGM3e0KlBm7VZRgYSCbY2Ze2PBHXdrUlPK4D/6b8= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727869621; c=relaxed/simple; bh=Xb8eImk55haK2XXhyREsN0eG3zAveMRBYGL3jSGF1ww=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=diQFPs129qKt6mR6SSR/qWY5mnvlkdLgMO6AI221JsKArbqt0YzGGB42LAd0oeVNSUBQADmUdUyKHCRZ/YgAB6ES6DxF/9OVvqW42yZO3pyp0zTYZknGJmXc++VVo92op4BTNJbSLAQaYP3P7ru+1zBk6HIgQFIDdgXw89Eo5U0= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=chromium.org; spf=pass smtp.mailfrom=chromium.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b=UoMAkzUu; arc=none smtp.client-ip=209.85.210.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=chromium.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=chromium.org header.i=@chromium.org header.b="UoMAkzUu" Received: by mail-pf1-f172.google.com with SMTP id d2e1a72fcca58-71970655611so6073729b3a.0 for ; Wed, 02 Oct 2024 04:46:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1727869619; x=1728474419; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=4eL/XnvWSRIF7ErhZle48teJZLAeJmMXd6nPwZPH1JI=; b=UoMAkzUu6rvO2IK6gpCJcqs+ffiD+QWDkLrfrZIIfM5FrPyNE9MxzQy/MK7gJQggkS uLt8y2Zm/KLWpcNJ0MwrUZhsmDhIZpP9MFPxL3SkoLJrknYJH1ewPt7QM85EZb+9tuFW Zc3fGAzNhPH9eWiD+TfVE3Ik5wjeQXkitYU1c= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1727869619; x=1728474419; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=4eL/XnvWSRIF7ErhZle48teJZLAeJmMXd6nPwZPH1JI=; b=Z4NLKQQ/mvYvooJ44rrnMF7T4Qclr8biNsK8rBhM9FoFR315PotF9DBHoqygPOi82Z W93RTEswNZkr70TL4BJfhpNJTgMdCHbDvqI4Ld3KpolOPn6aGJ50q/lHxvgw6bFy3CFx Yr6XDRdqzVuM4isbKXt0o4Ax+bYFUjY0t9cvOPv55KL/FnlSj6d2J6TxXOaD49K6nGZM rG99JinX3y9F1M0JCf0ZNLouJ2tfGUlGoswEJ0+I/dkJKez1WVFq5JL/vVIZ4U76BWKS ekXnRFsvJHgpq+GB/rVyEhcrCu29wQztt/pK+lVCN6GoYFClJdJ6Ut3RZqOGapdL8Idm ybiA== X-Forwarded-Encrypted: i=1; AJvYcCUfxogR2VCdM+xa0s3oGhlCIDW9n7SR3r99riQ5OtaFkb2XBuLebfr0Cd4NzBxzFisXOezNUeJCiket@vger.kernel.org X-Gm-Message-State: AOJu0YzL6NRGQR3YrYGa2WAMyjFZY1BU5XYvOQQtkTSJ2cH48pKxW/hg 8NtkbK4C4TK/godqYSAlvKJnnPVhQR234XbC4vgDqgJW3101YBRStuvJTRdHQA== X-Google-Smtp-Source: AGHT+IGlwXsLd9Mr6AKVcGBEFrntudbL/edWj37XdM8N2RuC+afWpz1Bv27KcrpodULuJDiUNFgDoQ== X-Received: by 2002:a05:6a00:9a0:b0:717:8da8:6ec1 with SMTP id d2e1a72fcca58-71dc5d425bcmr4815173b3a.17.1727869619267; Wed, 02 Oct 2024 04:46:59 -0700 (PDT) Received: from fshao-p620.tpe.corp.google.com ([2401:fa00:1:10:3bd0:d371:4a25:3576]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-71b2652baefsm9639627b3a.180.2024.10.02.04.46.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Oct 2024 04:46:58 -0700 (PDT) From: Fei Shao To: AngeloGioacchino Del Regno Cc: Fei Shao , Conor Dooley , Krzysztof Kozlowski , Matthias Brugger , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org Subject: [PATCH 4/9] arm64: dts: mediatek: mt8188: Add video decoder and encoder nodes Date: Wed, 2 Oct 2024 19:41:44 +0800 Message-ID: <20241002114614.847553-5-fshao@chromium.org> X-Mailer: git-send-email 2.46.1.824.gd892dcdcdd-goog In-Reply-To: <20241002114614.847553-1-fshao@chromium.org> References: <20241002114614.847553-1-fshao@chromium.org> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Add video decoder and encoder nodes for hardware-accelerated video decoding and encoding support. Signed-off-by: Fei Shao --- arch/arm64/boot/dts/mediatek/mt8188.dtsi | 83 ++++++++++++++++++++++++ 1 file changed, 83 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts/mediatek/mt8188.dtsi index ff639418bebe..dbea562ee8ba 100644 --- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi @@ -2181,6 +2181,64 @@ ccusys: clock-controller@17200000 { #clock-cells = <1>; }; + video_decoder: video-decoder@18000000 { + compatible = "mediatek,mt8188-vcodec-dec"; + reg = <0 0x18000000 0 0x1000>, <0 0x18004000 0 0x1000>; + ranges = <0 0 0 0x18000000 0 0x26000>; + iommus = <&vpp_iommu M4U_PORT_L23_HW_VDEC_UFO_ENC_EXT>; + #address-cells = <2>; + #size-cells = <2>; + mediatek,scp = <&scp>; + + video-codec@10000 { + compatible = "mediatek,mtk-vcodec-lat"; + reg = <0 0x10000 0 0x800>; + assigned-clocks = <&topckgen CLK_TOP_VDEC>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>; + clocks = <&topckgen CLK_TOP_VDEC>, + <&vdecsys_soc CLK_VDEC1_SOC_VDEC>, + <&vdecsys_soc CLK_VDEC1_SOC_LAT>, + <&topckgen CLK_TOP_UNIVPLL_D6>; + clock-names = "sel", "vdec", "lat", "top"; + interrupts = ; + iommus = <&vpp_iommu M4U_PORT_L23_HW_VDEC_LAT0_VLD_EXT>, + <&vpp_iommu M4U_PORT_L23_HW_VDEC_LAT0_VLD2_EXT>, + <&vpp_iommu M4U_PORT_L23_HW_VDEC_LAT0_AVC_MV_EXT>, + <&vpp_iommu M4U_PORT_L23_HW_VDEC_LAT0_PRED_RD_EXT>, + <&vpp_iommu M4U_PORT_L23_HW_VDEC_LAT0_TILE_EXT>, + <&vpp_iommu M4U_PORT_L23_HW_VDEC_LAT0_WDMA_EXT>, + <&vpp_iommu M4U_PORT_L23_HW_VDEC_UFO_ENC_EXT>, + <&vpp_iommu M4U_PORT_L23_HW_VDEC_UFO_ENC_EXT_C>, + <&vpp_iommu M4U_PORT_L23_HW_VDEC_MC_EXT_C>; + power-domains = <&spm MT8188_POWER_DOMAIN_VDEC0>; + }; + + video-codec@25000 { + compatible = "mediatek,mtk-vcodec-core"; + reg = <0 0x25000 0 0x1000>; + assigned-clocks = <&topckgen CLK_TOP_VDEC>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>; + clocks = <&topckgen CLK_TOP_VDEC>, + <&vdecsys CLK_VDEC2_VDEC>, + <&vdecsys CLK_VDEC2_LAT>, + <&topckgen CLK_TOP_UNIVPLL_D6>; + clock-names = "sel", "vdec", "lat", "top"; + interrupts = ; + iommus = <&vdo_iommu M4U_PORT_L21_HW_VDEC_MC_EXT>, + <&vdo_iommu M4U_PORT_L21_HW_VDEC_UFO_EXT>, + <&vdo_iommu M4U_PORT_L21_HW_VDEC_PP_EXT>, + <&vdo_iommu M4U_PORT_L21_HW_VDEC_PRED_RD_EXT>, + <&vdo_iommu M4U_PORT_L21_HW_VDEC_PRED_WR_EXT>, + <&vdo_iommu M4U_PORT_L21_HW_VDEC_PPWRAP_EXT>, + <&vdo_iommu M4U_PORT_L21_HW_VDEC_TILE_EXT>, + <&vdo_iommu M4U_PORT_L21_HW_VDEC_VLD_EXT>, + <&vdo_iommu M4U_PORT_L21_HW_VDEC_VLD2_EXT>, + <&vdo_iommu M4U_PORT_L21_HW_VDEC_AVC_MV_EXT>, + <&vdo_iommu M4U_PORT_L21_HW_VDEC_UFO_EXT_C>; + power-domains = <&spm MT8188_POWER_DOMAIN_VDEC1>; + }; + }; + larb23: smi@1800d000 { compatible = "mediatek,mt8188-smi-larb"; reg = <0 0x1800d000 0 0x1000>; @@ -2232,6 +2290,31 @@ larb19: smi@1a010000 { mediatek,smi = <&vdo_smi_common>; }; + video_encoder: video-encoder@1a020000 { + compatible = "mediatek,mt8188-vcodec-enc"; + reg = <0 0x1a020000 0 0x10000>; + #address-cells = <2>; + #size-cells = <2>; + assigned-clocks = <&topckgen CLK_TOP_VENC>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>; + clocks = <&vencsys CLK_VENC1_VENC>; + clock-names = "venc_sel"; + interrupts = ; + iommus = <&vdo_iommu M4U_PORT_L19_VENC_RCPU>, + <&vdo_iommu M4U_PORT_L19_VENC_REC>, + <&vdo_iommu M4U_PORT_L19_VENC_BSDMA>, + <&vdo_iommu M4U_PORT_L19_VENC_SV_COMV>, + <&vdo_iommu M4U_PORT_L19_VENC_RD_COMV>, + <&vdo_iommu M4U_PORT_L19_VENC_CUR_LUMA>, + <&vdo_iommu M4U_PORT_L19_VENC_CUR_CHROMA>, + <&vdo_iommu M4U_PORT_L19_VENC_REF_LUMA>, + <&vdo_iommu M4U_PORT_L19_VENC_REF_CHROMA>, + <&vdo_iommu M4U_PORT_L19_VENC_SUB_W_LUMA>, + <&vdo_iommu M4U_PORT_L19_VENC_SUB_R_LUMA>; + power-domains = <&spm MT8188_POWER_DOMAIN_VENC>; + mediatek,scp = <&scp>; + }; + disp_dsi: dsi@1c008000 { compatible = "mediatek,mt8188-dsi"; reg = <0 0x1c008000 0 0x1000>; -- 2.46.1.824.gd892dcdcdd-goog