[PATCH v2 net-next 0/2] make PHY output RMII reference clock

[PATCH v2 net-next 0/2] make PHY output RMII reference clock

[Wei Fang]

The TJA11xx PHYs have the capability to provide 50MHz reference clock
in RMII mode and output on REF_CLK pin. Therefore, add the new property
"nxp,rmii-refclk-output" to support this feature. This property is only
available for PHYs which use nxp-c45-tja11xx driver, such as TJA1103,
TJA1104, TJA1120 and TJA1121.

---
v2 Link: https://lore.kernel.org/netdev/20240823-jersey-conducive-70863dd6fd27@spud/T/
v3 Linl: https://lore.kernel.org/imx/20240826052700.232453-1-wei.fang@nxp.com/
---

Wei Fang (2):
  dt-bindings: net: tja11xx: add "nxp,rmii-refclk-out" property
  net: phy: c45-tja11xx: add support for outputing RMII reference clock

 .../devicetree/bindings/net/nxp,tja11xx.yaml  | 18 ++++++++++++
 drivers/net/phy/nxp-c45-tja11xx.c             | 29 +++++++++++++++++--
 drivers/net/phy/nxp-c45-tja11xx.h             |  1 +
 3 files changed, 46 insertions(+), 2 deletions(-)

-- 
2.34.1

[PATCH v2 net-next 1/2] dt-bindings: net: tja11xx: add "nxp,rmii-refclk-out" property

[Wei Fang]

Per the RMII specification, the REF_CLK is sourced from MAC to PHY
or from an external source. But for TJA11xx PHYs, they support to
output a 50MHz RMII reference clock on REF_CLK pin. Previously the
"nxp,rmii-refclk-in" was added to indicate that in RMII mode, if
this property is present, REF_CLK is input to the PHY, otherwise
it is output. This seems inappropriate now. Because according to
the RMII specification, the REF_CLK is originally input, so there
is no need to add an additional "nxp,rmii-refclk-in" property to
declare that REF_CLK is input.

Unfortunately, because the "nxp,rmii-refclk-in" property has been
added for a while, and we cannot confirm which DTS use the TJA1100
and TJA1101 PHYs, changing it to switch polarity will cause an ABI
break. But fortunately, this property is only valid for TJA1100 and
TJA1101. For TJA1103/TJA1104/TJA1120/TJA1121 PHYs, this property is
invalid because they use the nxp-c45-tja11xx driver, which is a
different driver from TJA1100/TJA1101. Therefore, for PHYs using
nxp-c45-tja11xx driver, add "nxp,rmii-refclk-out" property to
support outputting RMII reference clock on REF_CLK pin.

Signed-off-by: Wei Fang <wei.fang@nxp.com>
---
V2 changes:
1. Change the property name from "nxp,reverse-mode" to
"nxp,phy-output-refclk".
2. Simplify the description of the property.
3. Modify the subject and commit message.
V3 changes:
1. Keep the "nxp,rmii-refclk-in" property for TJA1100 and TJA1101.
2. Rephrase the commit message and subject.
V3 changes:
1. Change the property name from "nxp,phy-output-refclk" to
"nxp,rmii-refclk-out", which means the opposite of "nxp,rmii-refclk-in".
2. Refactor the patch after fixing the original issue with this YAML.
---
 .../devicetree/bindings/net/nxp,tja11xx.yaml   | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/Documentation/devicetree/bindings/net/nxp,tja11xx.yaml b/Documentation/devicetree/bindings/net/nxp,tja11xx.yaml
index a754a61adc2d..1e688c7a497d 100644
--- a/Documentation/devicetree/bindings/net/nxp,tja11xx.yaml
+++ b/Documentation/devicetree/bindings/net/nxp,tja11xx.yaml
@@ -62,6 +62,24 @@ allOf:
             reference clock output when RMII mode enabled.
             Only supported on TJA1100 and TJA1101.
 
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - ethernet-phy-id001b.b010
+              - ethernet-phy-id001b.b013
+              - ethernet-phy-id001b.b030
+              - ethernet-phy-id001b.b031
+
+    then:
+      properties:
+        nxp,rmii-refclk-out:
+          type: boolean
+          description: |
+            Enable 50MHz RMII reference clock output on REF_CLK pin. This
+            property is only applicable to nxp-c45-tja11xx driver.
+
 patternProperties:
   "^ethernet-phy@[0-9a-f]+$":
     type: object
-- 
2.34.1

Re: [PATCH v2 net-next 1/2] dt-bindings: net: tja11xx: add "nxp,rmii-refclk-out" property

[Rob Herring]

On Tue, Oct 08, 2024 at 03:07:07PM +0800, Wei Fang wrote:
> Per the RMII specification, the REF_CLK is sourced from MAC to PHY
> or from an external source. But for TJA11xx PHYs, they support to
> output a 50MHz RMII reference clock on REF_CLK pin. Previously the
> "nxp,rmii-refclk-in" was added to indicate that in RMII mode, if
> this property is present, REF_CLK is input to the PHY, otherwise
> it is output. This seems inappropriate now. Because according to
> the RMII specification, the REF_CLK is originally input, so there
> is no need to add an additional "nxp,rmii-refclk-in" property to
> declare that REF_CLK is input.
> 
> Unfortunately, because the "nxp,rmii-refclk-in" property has been
> added for a while, and we cannot confirm which DTS use the TJA1100
> and TJA1101 PHYs, changing it to switch polarity will cause an ABI
> break. But fortunately, this property is only valid for TJA1100 and
> TJA1101. For TJA1103/TJA1104/TJA1120/TJA1121 PHYs, this property is
> invalid because they use the nxp-c45-tja11xx driver, which is a
> different driver from TJA1100/TJA1101. Therefore, for PHYs using
> nxp-c45-tja11xx driver, add "nxp,rmii-refclk-out" property to
> support outputting RMII reference clock on REF_CLK pin.
> 
> Signed-off-by: Wei Fang <wei.fang@nxp.com>
> ---
> V2 changes:
> 1. Change the property name from "nxp,reverse-mode" to
> "nxp,phy-output-refclk".
> 2. Simplify the description of the property.
> 3. Modify the subject and commit message.
> V3 changes:
> 1. Keep the "nxp,rmii-refclk-in" property for TJA1100 and TJA1101.
> 2. Rephrase the commit message and subject.
> V3 changes:
> 1. Change the property name from "nxp,phy-output-refclk" to
> "nxp,rmii-refclk-out", which means the opposite of "nxp,rmii-refclk-in".
> 2. Refactor the patch after fixing the original issue with this YAML.
> ---
>  .../devicetree/bindings/net/nxp,tja11xx.yaml   | 18 ++++++++++++++++++
>  1 file changed, 18 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/net/nxp,tja11xx.yaml b/Documentation/devicetree/bindings/net/nxp,tja11xx.yaml
> index a754a61adc2d..1e688c7a497d 100644
> --- a/Documentation/devicetree/bindings/net/nxp,tja11xx.yaml
> +++ b/Documentation/devicetree/bindings/net/nxp,tja11xx.yaml
> @@ -62,6 +62,24 @@ allOf:
>              reference clock output when RMII mode enabled.
>              Only supported on TJA1100 and TJA1101.
>  
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            enum:
> +              - ethernet-phy-id001b.b010
> +              - ethernet-phy-id001b.b013
> +              - ethernet-phy-id001b.b030
> +              - ethernet-phy-id001b.b031
> +
> +    then:
> +      properties:
> +        nxp,rmii-refclk-out:
> +          type: boolean
> +          description: |

Don't need '|' if no formatting.

> +            Enable 50MHz RMII reference clock output on REF_CLK pin. This
> +            property is only applicable to nxp-c45-tja11xx driver.

Reword this to not be about some driver.

> +
>  patternProperties:
>    "^ethernet-phy@[0-9a-f]+$":
>      type: object
> -- 
> 2.34.1
> 

RE: [PATCH v2 net-next 1/2] dt-bindings: net: tja11xx: add "nxp,rmii-refclk-out" property

[Wei Fang]

> -----Original Message-----
> From: Rob Herring <robh@kernel.org>
> Sent: 2024年10月9日 23:12
> To: Wei Fang <wei.fang@nxp.com>
> Cc: davem@davemloft.net; edumazet@google.com; kuba@kernel.org;
> pabeni@redhat.com; krzk+dt@kernel.org; conor+dt@kernel.org;
> andrew@lunn.ch; f.fainelli@gmail.com; hkallweit1@gmail.com; Andrei Botila
> (OSS) <andrei.botila@oss.nxp.com>; linux@armlinux.org.uk;
> devicetree@vger.kernel.org; linux-kernel@vger.kernel.org;
> netdev@vger.kernel.org; imx@lists.linux.dev
> Subject: Re: [PATCH v2 net-next 1/2] dt-bindings: net: tja11xx: add
> "nxp,rmii-refclk-out" property
> 
> On Tue, Oct 08, 2024 at 03:07:07PM +0800, Wei Fang wrote:
> > Per the RMII specification, the REF_CLK is sourced from MAC to PHY or
> > from an external source. But for TJA11xx PHYs, they support to output
> > a 50MHz RMII reference clock on REF_CLK pin. Previously the
> > "nxp,rmii-refclk-in" was added to indicate that in RMII mode, if this
> > property is present, REF_CLK is input to the PHY, otherwise it is
> > output. This seems inappropriate now. Because according to the RMII
> > specification, the REF_CLK is originally input, so there is no need to
> > add an additional "nxp,rmii-refclk-in" property to declare that
> > REF_CLK is input.
> >
> > Unfortunately, because the "nxp,rmii-refclk-in" property has been
> > added for a while, and we cannot confirm which DTS use the TJA1100 and
> > TJA1101 PHYs, changing it to switch polarity will cause an ABI break.
> > But fortunately, this property is only valid for TJA1100 and TJA1101.
> > For TJA1103/TJA1104/TJA1120/TJA1121 PHYs, this property is invalid
> > because they use the nxp-c45-tja11xx driver, which is a different
> > driver from TJA1100/TJA1101. Therefore, for PHYs using nxp-c45-tja11xx
> > driver, add "nxp,rmii-refclk-out" property to support outputting RMII
> > reference clock on REF_CLK pin.
> >
> > Signed-off-by: Wei Fang <wei.fang@nxp.com>
> > ---
> > V2 changes:
> > 1. Change the property name from "nxp,reverse-mode" to
> > "nxp,phy-output-refclk".
> > 2. Simplify the description of the property.
> > 3. Modify the subject and commit message.
> > V3 changes:
> > 1. Keep the "nxp,rmii-refclk-in" property for TJA1100 and TJA1101.
> > 2. Rephrase the commit message and subject.
> > V3 changes:
> > 1. Change the property name from "nxp,phy-output-refclk" to
> > "nxp,rmii-refclk-out", which means the opposite of "nxp,rmii-refclk-in".
> > 2. Refactor the patch after fixing the original issue with this YAML.
> > ---
> >  .../devicetree/bindings/net/nxp,tja11xx.yaml   | 18 ++++++++++++++++++
> >  1 file changed, 18 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/net/nxp,tja11xx.yaml
> > b/Documentation/devicetree/bindings/net/nxp,tja11xx.yaml
> > index a754a61adc2d..1e688c7a497d 100644
> > --- a/Documentation/devicetree/bindings/net/nxp,tja11xx.yaml
> > +++ b/Documentation/devicetree/bindings/net/nxp,tja11xx.yaml
> > @@ -62,6 +62,24 @@ allOf:
> >              reference clock output when RMII mode enabled.
> >              Only supported on TJA1100 and TJA1101.
> >
> > +  - if:
> > +      properties:
> > +        compatible:
> > +          contains:
> > +            enum:
> > +              - ethernet-phy-id001b.b010
> > +              - ethernet-phy-id001b.b013
> > +              - ethernet-phy-id001b.b030
> > +              - ethernet-phy-id001b.b031
> > +
> > +    then:
> > +      properties:
> > +        nxp,rmii-refclk-out:
> > +          type: boolean
> > +          description: |
> 
> Don't need '|' if no formatting.
> 
> > +            Enable 50MHz RMII reference clock output on REF_CLK pin.
> This
> > +            property is only applicable to nxp-c45-tja11xx driver.
> 
> Reword this to not be about some driver.

Thanks, I will refine it
> 
> > +
> >  patternProperties:
> >    "^ethernet-phy@[0-9a-f]+$":
> >      type: object
> > --
> > 2.34.1
> >

[PATCH v2 net-next 2/2] net: phy: c45-tja11xx: add support for outputing RMII reference clock

[Wei Fang]

For TJA11xx PHYs, they have the capability to output 50MHz reference
clock on REF_CLK pin in RMII mode, which is called "revRMII" mode in
the PHY data sheet.

Signed-off-by: Wei Fang <wei.fang@nxp.com>
---
V2 changes:
1. Change the property name.
2. Modify the subject and commit message.
V3 changes:
No changes.
V4 changes:
1. Change the property name based on patch 1.
---
 drivers/net/phy/nxp-c45-tja11xx.c | 29 +++++++++++++++++++++++++++--
 drivers/net/phy/nxp-c45-tja11xx.h |  1 +
 2 files changed, 28 insertions(+), 2 deletions(-)

diff --git a/drivers/net/phy/nxp-c45-tja11xx.c b/drivers/net/phy/nxp-c45-tja11xx.c
index 5af5ade4fc64..3fe630a72ff1 100644
--- a/drivers/net/phy/nxp-c45-tja11xx.c
+++ b/drivers/net/phy/nxp-c45-tja11xx.c
@@ -10,6 +10,7 @@
 #include <linux/kernel.h>
 #include <linux/mii.h>
 #include <linux/module.h>
+#include <linux/of.h>
 #include <linux/phy.h>
 #include <linux/processor.h>
 #include <linux/property.h>
@@ -185,6 +186,8 @@
 
 #define NXP_C45_SKB_CB(skb)	((struct nxp_c45_skb_cb *)(skb)->cb)
 
+#define TJA11XX_REVERSE_MODE		BIT(0)
+
 struct nxp_c45_phy;
 
 struct nxp_c45_skb_cb {
@@ -1510,6 +1513,7 @@ static int nxp_c45_get_delays(struct phy_device *phydev)
 
 static int nxp_c45_set_phy_mode(struct phy_device *phydev)
 {
+	struct nxp_c45_phy *priv = phydev->priv;
 	int ret;
 
 	ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_ABILITIES);
@@ -1561,8 +1565,13 @@ static int nxp_c45_set_phy_mode(struct phy_device *phydev)
 			phydev_err(phydev, "rmii mode not supported\n");
 			return -EINVAL;
 		}
-		phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_MII_BASIC_CONFIG,
-			      MII_BASIC_CONFIG_RMII);
+
+		if (priv->flags & TJA11XX_REVERSE_MODE)
+			phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_MII_BASIC_CONFIG,
+				      MII_BASIC_CONFIG_RMII | MII_BASIC_CONFIG_REV);
+		else
+			phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_MII_BASIC_CONFIG,
+				      MII_BASIC_CONFIG_RMII);
 		break;
 	case PHY_INTERFACE_MODE_SGMII:
 		if (!(ret & SGMII_ABILITY)) {
@@ -1623,6 +1632,20 @@ static int nxp_c45_get_features(struct phy_device *phydev)
 	return genphy_c45_pma_read_abilities(phydev);
 }
 
+static int nxp_c45_parse_dt(struct phy_device *phydev)
+{
+	struct device_node *node = phydev->mdio.dev.of_node;
+	struct nxp_c45_phy *priv = phydev->priv;
+
+	if (!IS_ENABLED(CONFIG_OF_MDIO))
+		return 0;
+
+	if (of_property_read_bool(node, "nxp,rmii-refclk-out"))
+		priv->flags |= TJA11XX_REVERSE_MODE;
+
+	return 0;
+}
+
 static int nxp_c45_probe(struct phy_device *phydev)
 {
 	struct nxp_c45_phy *priv;
@@ -1642,6 +1665,8 @@ static int nxp_c45_probe(struct phy_device *phydev)
 
 	phydev->priv = priv;
 
+	nxp_c45_parse_dt(phydev);
+
 	mutex_init(&priv->ptp_lock);
 
 	phy_abilities = phy_read_mmd(phydev, MDIO_MMD_VEND1,
diff --git a/drivers/net/phy/nxp-c45-tja11xx.h b/drivers/net/phy/nxp-c45-tja11xx.h
index f364fca68f0b..8b5fc383752b 100644
--- a/drivers/net/phy/nxp-c45-tja11xx.h
+++ b/drivers/net/phy/nxp-c45-tja11xx.h
@@ -28,6 +28,7 @@ struct nxp_c45_phy {
 	int extts_index;
 	bool extts;
 	struct nxp_c45_macsec *macsec;
+	u32 flags;
 };
 
 #if IS_ENABLED(CONFIG_MACSEC)
-- 
2.34.1

Re: [PATCH v2 net-next 2/2] net: phy: c45-tja11xx: add support for outputing RMII reference clock

[Russell King (Oracle)]

On Tue, Oct 08, 2024 at 03:07:08PM +0800, Wei Fang wrote:
> @@ -1561,8 +1565,13 @@ static int nxp_c45_set_phy_mode(struct phy_device *phydev)
>  			phydev_err(phydev, "rmii mode not supported\n");
>  			return -EINVAL;
>  		}
> -		phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_MII_BASIC_CONFIG,
> -			      MII_BASIC_CONFIG_RMII);
> +
> +		if (priv->flags & TJA11XX_REVERSE_MODE)
> +			phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_MII_BASIC_CONFIG,
> +				      MII_BASIC_CONFIG_RMII | MII_BASIC_CONFIG_REV);
> +		else
> +			phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_MII_BASIC_CONFIG,
> +				      MII_BASIC_CONFIG_RMII);

Netdev has an 80 column limit, and this needs commenting because we have
PHY_INTERFACE_MODE_REVRMII which could be confused with this (although
I haven't checked.)

		u16 basic_config;
		...
		basic_config = MII_BASIC_CONFIG_RMII;

		/* This is not PHY_INTERFACE_MODE_REVRMII */
		if (priv->flags & TJA11XX_REVERSE_MODE)
			basic_config |= MII_BASIC_CONFIG_REV;

		phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_MII_BASIC_CONFIG,
			      basic_config);

is much nicer to read.

Thanks.

-- 
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTP is here! 80Mbps down 10Mbps up. Decent connectivity at last!

RE: [PATCH v2 net-next 2/2] net: phy: c45-tja11xx: add support for outputing RMII reference clock

[Wei Fang]

> -----Original Message-----
> From: Russell King <linux@armlinux.org.uk>
> Sent: 2024年10月8日 16:31
> To: Wei Fang <wei.fang@nxp.com>
> Cc: davem@davemloft.net; edumazet@google.com; kuba@kernel.org;
> pabeni@redhat.com; robh@kernel.org; krzk+dt@kernel.org;
> conor+dt@kernel.org; andrew@lunn.ch; f.fainelli@gmail.com;
> hkallweit1@gmail.com; Andrei Botila (OSS) <andrei.botila@oss.nxp.com>;
> devicetree@vger.kernel.org; linux-kernel@vger.kernel.org;
> netdev@vger.kernel.org; imx@lists.linux.dev
> Subject: Re: [PATCH v2 net-next 2/2] net: phy: c45-tja11xx: add support for
> outputing RMII reference clock
> 
> On Tue, Oct 08, 2024 at 03:07:08PM +0800, Wei Fang wrote:
> > @@ -1561,8 +1565,13 @@ static int nxp_c45_set_phy_mode(struct
> phy_device *phydev)
> >  			phydev_err(phydev, "rmii mode not supported\n");
> >  			return -EINVAL;
> >  		}
> > -		phy_write_mmd(phydev, MDIO_MMD_VEND1,
> VEND1_MII_BASIC_CONFIG,
> > -			      MII_BASIC_CONFIG_RMII);
> > +
> > +		if (priv->flags & TJA11XX_REVERSE_MODE)
> > +			phy_write_mmd(phydev, MDIO_MMD_VEND1,
> VEND1_MII_BASIC_CONFIG,
> > +				      MII_BASIC_CONFIG_RMII |
> MII_BASIC_CONFIG_REV);
> > +		else
> > +			phy_write_mmd(phydev, MDIO_MMD_VEND1,
> VEND1_MII_BASIC_CONFIG,
> > +				      MII_BASIC_CONFIG_RMII);
> 
> Netdev has an 80 column limit, and this needs commenting because we have
> PHY_INTERFACE_MODE_REVRMII which could be confused with this (although
> I haven't checked.)
> 
> 		u16 basic_config;
> 		...
> 		basic_config = MII_BASIC_CONFIG_RMII;
> 
> 		/* This is not PHY_INTERFACE_MODE_REVRMII */
> 		if (priv->flags & TJA11XX_REVERSE_MODE)
> 			basic_config |= MII_BASIC_CONFIG_REV;
> 
> 		phy_write_mmd(phydev, MDIO_MMD_VEND1,
> VEND1_MII_BASIC_CONFIG,
> 			      basic_config);
> 
> is much nicer to read.
> 

Okay, I will refine the patch, thanks!

Re: [PATCH v2 net-next 2/2] net: phy: c45-tja11xx: add support for outputing RMII reference clock

[Simon Horman]

On Tue, Oct 08, 2024 at 03:07:08PM +0800, Wei Fang wrote:
> For TJA11xx PHYs, they have the capability to output 50MHz reference
> clock on REF_CLK pin in RMII mode, which is called "revRMII" mode in
> the PHY data sheet.
> 
> Signed-off-by: Wei Fang <wei.fang@nxp.com>

Hi,

As it looks like there will be a v3 anyway,
please consider correcting the spelling of outputting in the subject.

Thanks!

RE: [PATCH v2 net-next 2/2] net: phy: c45-tja11xx: add support for outputing RMII reference clock

[Wei Fang]

> -----Original Message-----
> From: Simon Horman <horms@kernel.org>
> Sent: 2024年10月9日 19:58
> To: Wei Fang <wei.fang@nxp.com>
> Cc: davem@davemloft.net; edumazet@google.com; kuba@kernel.org;
> pabeni@redhat.com; robh@kernel.org; krzk+dt@kernel.org;
> conor+dt@kernel.org; andrew@lunn.ch; f.fainelli@gmail.com;
> hkallweit1@gmail.com; Andrei Botila (OSS) <andrei.botila@oss.nxp.com>;
> linux@armlinux.org.uk; devicetree@vger.kernel.org;
> linux-kernel@vger.kernel.org; netdev@vger.kernel.org; imx@lists.linux.dev
> Subject: Re: [PATCH v2 net-next 2/2] net: phy: c45-tja11xx: add support for
> outputing RMII reference clock
> 
> On Tue, Oct 08, 2024 at 03:07:08PM +0800, Wei Fang wrote:
> > For TJA11xx PHYs, they have the capability to output 50MHz reference
> > clock on REF_CLK pin in RMII mode, which is called "revRMII" mode in
> > the PHY data sheet.
> >
> > Signed-off-by: Wei Fang <wei.fang@nxp.com>
> 
> Hi,
> 
> As it looks like there will be a v3 anyway,
> please consider correcting the spelling of outputting in the subject.
> 
> Thanks!

Thanks for pointing this typo, I will correct it in next version.

RE: [PATCH v2 net-next 0/2] make PHY output RMII reference clock

[Wei Fang]

> -----Original Message-----
> From: Wei Fang
> Sent: 2024年10月8日 15:24
> To: davem@davemloft.net; edumazet@google.com; kuba@kernel.org;
> pabeni@redhat.com; robh@kernel.org; krzk+dt@kernel.org;
> conor+dt@kernel.org; andrew@lunn.ch; f.fainelli@gmail.com;
> hkallweit1@gmail.com; Andrei Botila (OSS) <andrei.botila@oss.nxp.com>;
> linux@armlinux.org.uk
> Cc: devicetree@vger.kernel.org; linux-kernel@vger.kernel.org;
> netdev@vger.kernel.org; imx@lists.linux.dev
> Subject: [PATCH v2 net-next 0/2] make PHY output RMII reference clock
> 
> The TJA11xx PHYs have the capability to provide 50MHz reference clock
> in RMII mode and output on REF_CLK pin. Therefore, add the new property
> "nxp,rmii-refclk-output" to support this feature. This property is only
> available for PHYs which use nxp-c45-tja11xx driver, such as TJA1103,
> TJA1104, TJA1120 and TJA1121.
> 
> ---
> v2 Link:
> https://lore.kernel.org/netdev/20240823-jersey-conducive-70863dd6fd27@spu
> d/T/
> v3 Linl:
> https://lore.kernel.org/imx/20240826052700.232453-1-wei.fang@nxp.com/
> ---
> 
> Wei Fang (2):
>   dt-bindings: net: tja11xx: add "nxp,rmii-refclk-out" property
>   net: phy: c45-tja11xx: add support for outputing RMII reference clock
> 
>  .../devicetree/bindings/net/nxp,tja11xx.yaml  | 18 ++++++++++++
>  drivers/net/phy/nxp-c45-tja11xx.c             | 29 +++++++++++++++++--
>  drivers/net/phy/nxp-c45-tja11xx.h             |  1 +
>  3 files changed, 46 insertions(+), 2 deletions(-)
> 
> --
> 2.34.1

Sorry for the wrong "v2" descriptor in the tile, it should be "v4". :(