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AJvYcCVbs2PRj6gciMRYVvx/sa0xcb0AMGScvePlcI2J+ptywICbld1rRS34uzC8nM7TGHC3LxQtV2ODYLvZ@vger.kernel.org X-Gm-Message-State: AOJu0YzgjtYrncP5JmR4a3DInaAVyXe7IfMYsXsA9a/8qVSoxFGu7F5T PInMxLG1VmxTp4RcMI8MK3QkCMd+FPbk6q8WALocX4usvIlmzxrRMURWy7Dxqw== X-Google-Smtp-Source: AGHT+IG3+r83KQNXnWosd0zcqE7RKm9feBt+w6DxilqXMW2DnNTwgYlUcNcUO4f60tmPSc9Bx2nQJQ== X-Received: by 2002:a17:90a:c08a:b0:2e2:c1d0:68dc with SMTP id 98e67ed59e1d1-2e2c8057f3dmr3466283a91.9.1728543809391; Thu, 10 Oct 2024 00:03:29 -0700 (PDT) Received: from thinkpad ([220.158.156.184]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2e2d5df1133sm568989a91.15.2024.10.10.00.03.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Oct 2024 00:03:28 -0700 (PDT) Date: Thu, 10 Oct 2024 12:33:23 +0530 From: Manivannan Sadhasivam To: Damien Le Moal Cc: Lorenzo Pieralisi , Kishon Vijay Abraham I , Shawn Lin , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Bjorn Helgaas , Heiko Stuebner , linux-pci@vger.kernel.org, Rob Herring , Krzysztof Kozlowski , Conor Dooley , devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org, Rick Wertenbroek , Wilfred Mallawa , Niklas Cassel Subject: Re: [PATCH v3 02/12] PCI: rockchip-ep: Use a macro to define EP controller .align feature Message-ID: <20241010070323.mxmvsn2vlprzidh3@thinkpad> References: <20241007041218.157516-1-dlemoal@kernel.org> <20241007041218.157516-3-dlemoal@kernel.org> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20241007041218.157516-3-dlemoal@kernel.org> On Mon, Oct 07, 2024 at 01:12:08PM +0900, Damien Le Moal wrote: > Introduce the macro ROCKCHIP_PCIE_AT_SIZE_ALIGN defined using > ROCKCHIP_PCIE_AT_MIN_NUM_BITS to initialize the .align field of the > controller epc_features structure, avoiding using the "magic" value 8 > directly. > > Signed-off-by: Damien Le Moal Reviewed-by: Manivannan Sadhasivam - Mani > --- > drivers/pci/controller/pcie-rockchip-ep.c | 2 +- > drivers/pci/controller/pcie-rockchip.h | 1 + > 2 files changed, 2 insertions(+), 1 deletion(-) > > diff --git a/drivers/pci/controller/pcie-rockchip-ep.c b/drivers/pci/controller/pcie-rockchip-ep.c > index 27a7febb74e0..5a07084fb7c4 100644 > --- a/drivers/pci/controller/pcie-rockchip-ep.c > +++ b/drivers/pci/controller/pcie-rockchip-ep.c > @@ -446,7 +446,7 @@ static const struct pci_epc_features rockchip_pcie_epc_features = { > .linkup_notifier = false, > .msi_capable = true, > .msix_capable = false, > - .align = 256, > + .align = ROCKCHIP_PCIE_AT_SIZE_ALIGN, > }; > > static const struct pci_epc_features* > diff --git a/drivers/pci/controller/pcie-rockchip.h b/drivers/pci/controller/pcie-rockchip.h > index 15ee949f2485..02368ce9bd54 100644 > --- a/drivers/pci/controller/pcie-rockchip.h > +++ b/drivers/pci/controller/pcie-rockchip.h > @@ -248,6 +248,7 @@ > > #define ROCKCHIP_PCIE_AT_MIN_NUM_BITS 8 > #define ROCKCHIP_PCIE_AT_MAX_NUM_BITS 20 > +#define ROCKCHIP_PCIE_AT_SIZE_ALIGN (1UL << ROCKCHIP_PCIE_AT_MIN_NUM_BITS) > > #define ROCKCHIP_PCIE_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar) \ > (PCIE_CORE_AXI_CONF_BASE + 0x0828 + (fn) * 0x0040 + (bar) * 0x0008) > -- > 2.46.2 > -- மணிவண்ணன் சதாசிவம்