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AJvYcCVzmJUKaeKOpY8pxAOeL/+g98TL/Wl9AV3Cc99nnsQPF+wap7PvAVDqGUOLRVhvhQ/F+J+ZJDb8i02t@vger.kernel.org X-Gm-Message-State: AOJu0YwYcs+EMcQ81BfTo1I3KvpFZAmGbnzthZWh0GesBrxeS5DHTIWC QJDU8X3I5DuullnApuJbuEjS1nQLqHY/AdRHYPCuFXkWpf4UD6THW9muPKG5Dg== X-Google-Smtp-Source: AGHT+IEhI0oEHMpvi/Ep8rZT37rMBupuv4nErdDsje5nS4NaslF2zKOn4ZDc5nilfaVzbMlP4HVL5w== X-Received: by 2002:a17:903:124b:b0:206:9a3f:15e5 with SMTP id d9443c01a7336-20c63746cafmr77627535ad.32.1728547802706; Thu, 10 Oct 2024 01:10:02 -0700 (PDT) Received: from thinkpad ([220.158.156.184]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20c8bad33d6sm5162345ad.33.2024.10.10.01.09.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Oct 2024 01:10:02 -0700 (PDT) Date: Thu, 10 Oct 2024 13:39:56 +0530 From: Manivannan Sadhasivam To: Damien Le Moal Cc: Lorenzo Pieralisi , Kishon Vijay Abraham I , Shawn Lin , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Bjorn Helgaas , Heiko Stuebner , linux-pci@vger.kernel.org, Rob Herring , Krzysztof Kozlowski , Conor Dooley , devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org, Rick Wertenbroek , Wilfred Mallawa , Niklas Cassel Subject: Re: [PATCH v3 07/12] PCI: rockchip-ep: Refactor rockchip_pcie_ep_probe() MSI-X hiding Message-ID: <20241010080956.z3cw2mxxlgrjafhs@thinkpad> References: <20241007041218.157516-1-dlemoal@kernel.org> <20241007041218.157516-8-dlemoal@kernel.org> <20241010072512.f7e4kdqcfe5okcvg@thinkpad> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20241010072512.f7e4kdqcfe5okcvg@thinkpad> On Thu, Oct 10, 2024 at 12:55:12PM +0530, Manivannan Sadhasivam wrote: > On Mon, Oct 07, 2024 at 01:12:13PM +0900, Damien Le Moal wrote: > > Move the code in rockchip_pcie_ep_probe() to hide the MSI-X capability > > to its own function, rockchip_pcie_ep_hide_msix_cap(). No functional > > changes. > > > > Signed-off-by: Damien Le Moal > > Reviewed-by: Manivannan Sadhasivam > > Btw, can someone from Rockchip confirm if this hiding is necessary for all the > SoCs? It looks to me like an SoC quirk. > > - Mani > > > --- > > drivers/pci/controller/pcie-rockchip-ep.c | 54 +++++++++++++---------- > > 1 file changed, 30 insertions(+), 24 deletions(-) > > > > diff --git a/drivers/pci/controller/pcie-rockchip-ep.c b/drivers/pci/controller/pcie-rockchip-ep.c > > index 523e9cdfd241..7a1798fcc2ad 100644 > > --- a/drivers/pci/controller/pcie-rockchip-ep.c > > +++ b/drivers/pci/controller/pcie-rockchip-ep.c > > @@ -581,6 +581,34 @@ static void rockchip_pcie_ep_release_resources(struct rockchip_pcie_ep *ep) > > pci_epc_mem_exit(ep->epc); > > } > > > > +static void rockchip_pcie_ep_hide_msix_cap(struct rockchip_pcie *rockchip) Perhaps a better name would be rockchip_pcie_disable_broken_msix()? As the function essentially disables MSIx which is broken. Again, it'd be good to know if this applies to all SoCs or just a few. - Mani > > +{ > > + u32 cfg_msi, cfg_msix_cp; > > + > > + /* > > + * MSI-X is not supported but the controller still advertises the MSI-X > > + * capability by default, which can lead to the Root Complex side > > + * allocating MSI-X vectors which cannot be used. Avoid this by skipping > > + * the MSI-X capability entry in the PCIe capabilities linked-list: get > > + * the next pointer from the MSI-X entry and set that in the MSI > > + * capability entry (which is the previous entry). This way the MSI-X > > + * entry is skipped (left out of the linked-list) and not advertised. > > + */ > > + cfg_msi = rockchip_pcie_read(rockchip, PCIE_EP_CONFIG_BASE + > > + ROCKCHIP_PCIE_EP_MSI_CTRL_REG); > > + > > + cfg_msi &= ~ROCKCHIP_PCIE_EP_MSI_CP1_MASK; > > + > > + cfg_msix_cp = rockchip_pcie_read(rockchip, PCIE_EP_CONFIG_BASE + > > + ROCKCHIP_PCIE_EP_MSIX_CAP_REG) & > > + ROCKCHIP_PCIE_EP_MSIX_CAP_CP_MASK; > > + > > + cfg_msi |= cfg_msix_cp; > > + > > + rockchip_pcie_write(rockchip, cfg_msi, > > + PCIE_EP_CONFIG_BASE + ROCKCHIP_PCIE_EP_MSI_CTRL_REG); > > +} > > + > > static int rockchip_pcie_ep_probe(struct platform_device *pdev) > > { > > struct device *dev = &pdev->dev; > > @@ -588,7 +616,6 @@ static int rockchip_pcie_ep_probe(struct platform_device *pdev) > > struct rockchip_pcie *rockchip; > > struct pci_epc *epc; > > int err; > > - u32 cfg_msi, cfg_msix_cp; > > > > ep = devm_kzalloc(dev, sizeof(*ep), GFP_KERNEL); > > if (!ep) > > @@ -619,6 +646,8 @@ static int rockchip_pcie_ep_probe(struct platform_device *pdev) > > if (err) > > goto err_disable_clocks; > > > > + rockchip_pcie_ep_hide_msix_cap(rockchip); > > + > > /* Establish the link automatically */ > > rockchip_pcie_write(rockchip, PCIE_CLIENT_LINK_TRAIN_ENABLE, > > PCIE_CLIENT_CONFIG); > > @@ -626,29 +655,6 @@ static int rockchip_pcie_ep_probe(struct platform_device *pdev) > > /* Only enable function 0 by default */ > > rockchip_pcie_write(rockchip, BIT(0), PCIE_CORE_PHY_FUNC_CFG); > > > > - /* > > - * MSI-X is not supported but the controller still advertises the MSI-X > > - * capability by default, which can lead to the Root Complex side > > - * allocating MSI-X vectors which cannot be used. Avoid this by skipping > > - * the MSI-X capability entry in the PCIe capabilities linked-list: get > > - * the next pointer from the MSI-X entry and set that in the MSI > > - * capability entry (which is the previous entry). This way the MSI-X > > - * entry is skipped (left out of the linked-list) and not advertised. > > - */ > > - cfg_msi = rockchip_pcie_read(rockchip, PCIE_EP_CONFIG_BASE + > > - ROCKCHIP_PCIE_EP_MSI_CTRL_REG); > > - > > - cfg_msi &= ~ROCKCHIP_PCIE_EP_MSI_CP1_MASK; > > - > > - cfg_msix_cp = rockchip_pcie_read(rockchip, PCIE_EP_CONFIG_BASE + > > - ROCKCHIP_PCIE_EP_MSIX_CAP_REG) & > > - ROCKCHIP_PCIE_EP_MSIX_CAP_CP_MASK; > > - > > - cfg_msi |= cfg_msix_cp; > > - > > - rockchip_pcie_write(rockchip, cfg_msi, > > - PCIE_EP_CONFIG_BASE + ROCKCHIP_PCIE_EP_MSI_CTRL_REG); > > - > > rockchip_pcie_write(rockchip, PCIE_CLIENT_CONF_ENABLE, > > PCIE_CLIENT_CONFIG); > > > > -- > > 2.46.2 > > > > -- > மணிவண்ணன் சதாசிவம் -- மணிவண்ணன் சதாசிவம்