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AJvYcCW1Kr8TENY46IX7rcL8teHSAnOJBL7VtKnZGdX3MPbtkigBK19r25ddSOLRS+jIEMUUQQOIg/fjN0yP@vger.kernel.org X-Gm-Message-State: AOJu0Yx3gAOb8MXi9Dsdxn9K+rOTdX7RAXyDTGnsMvtNIY9cVLL9O5AD HiZrLmHpBDwnEv3UJmL8pQPH74rt/DRo0D+pDsAutd756OHu1Kdh6v8XzlX7Lw== X-Google-Smtp-Source: AGHT+IFzZHkwvdoVYUTrMClpey36bmT0c8R68OOWU2q2z8TBVcF9DQcAzhzfY9NVpI7L4XVQJ154Rg== X-Received: by 2002:a05:6a20:9f0a:b0:1cf:2bb8:f38b with SMTP id adf61e73a8af0-1d8a3c4e2a7mr7301538637.38.1728548700720; Thu, 10 Oct 2024 01:25:00 -0700 (PDT) Received: from thinkpad ([220.158.156.184]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-71e2ab109e4sm572704b3a.206.2024.10.10.01.24.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Oct 2024 01:25:00 -0700 (PDT) Date: Thu, 10 Oct 2024 13:54:54 +0530 From: Manivannan Sadhasivam To: Damien Le Moal Cc: Lorenzo Pieralisi , Kishon Vijay Abraham I , Shawn Lin , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Bjorn Helgaas , Heiko Stuebner , linux-pci@vger.kernel.org, Rob Herring , Krzysztof Kozlowski , Conor Dooley , devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org, Rick Wertenbroek , Wilfred Mallawa , Niklas Cassel Subject: Re: [PATCH v3 09/12] PCI: rockship-ep: Introduce rockchip_pcie_ep_stop() Message-ID: <20241010082454.bkmqh7h3jctvtj27@thinkpad> References: <20241007041218.157516-1-dlemoal@kernel.org> <20241007041218.157516-10-dlemoal@kernel.org> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20241007041218.157516-10-dlemoal@kernel.org> I think the subject should reflect callback implementation. Like, PCI: rockchip-ep: Implement pci_epc_ops::stop_link() callback On Mon, Oct 07, 2024 at 01:12:15PM +0900, Damien Le Moal wrote: > Define the EPC operation ->stop for the rockchip endpoint driver with > the function rockchip_pcie_ep_stop(). This function disables link > training and the controller configuration, as the reverse to what > the start operation defined with rockchip_pcie_ep_start() does. > > Signed-off-by: Damien Le Moal Reviewed-by: Manivannan Sadhasivam - Mani > --- > drivers/pci/controller/pcie-rockchip-ep.c | 13 +++++++++++++ > drivers/pci/controller/pcie-rockchip.h | 1 + > 2 files changed, 14 insertions(+) > > diff --git a/drivers/pci/controller/pcie-rockchip-ep.c b/drivers/pci/controller/pcie-rockchip-ep.c > index 99f26f4a485b..a801e040bcad 100644 > --- a/drivers/pci/controller/pcie-rockchip-ep.c > +++ b/drivers/pci/controller/pcie-rockchip-ep.c > @@ -468,6 +468,18 @@ static int rockchip_pcie_ep_start(struct pci_epc *epc) > return 0; > } > > +static void rockchip_pcie_ep_stop(struct pci_epc *epc) > +{ > + struct rockchip_pcie_ep *ep = epc_get_drvdata(epc); > + struct rockchip_pcie *rockchip = &ep->rockchip; > + > + /* Stop link training and disable configuration */ > + rockchip_pcie_write(rockchip, > + PCIE_CLIENT_CONF_DISABLE | > + PCIE_CLIENT_LINK_TRAIN_DISABLE, > + PCIE_CLIENT_CONFIG); > +} > + > static const struct pci_epc_features rockchip_pcie_epc_features = { > .linkup_notifier = false, > .msi_capable = true, > @@ -492,6 +504,7 @@ static const struct pci_epc_ops rockchip_pcie_epc_ops = { > .get_msi = rockchip_pcie_ep_get_msi, > .raise_irq = rockchip_pcie_ep_raise_irq, > .start = rockchip_pcie_ep_start, > + .stop = rockchip_pcie_ep_stop, > .get_features = rockchip_pcie_ep_get_features, > }; > > diff --git a/drivers/pci/controller/pcie-rockchip.h b/drivers/pci/controller/pcie-rockchip.h > index 30398156095f..0263f158ee8d 100644 > --- a/drivers/pci/controller/pcie-rockchip.h > +++ b/drivers/pci/controller/pcie-rockchip.h > @@ -32,6 +32,7 @@ > #define PCIE_CLIENT_CONF_ENABLE HIWORD_UPDATE_BIT(0x0001) > #define PCIE_CLIENT_CONF_DISABLE HIWORD_UPDATE(0x0001, 0) > #define PCIE_CLIENT_LINK_TRAIN_ENABLE HIWORD_UPDATE_BIT(0x0002) > +#define PCIE_CLIENT_LINK_TRAIN_DISABLE HIWORD_UPDATE(0x0002, 0) > #define PCIE_CLIENT_ARI_ENABLE HIWORD_UPDATE_BIT(0x0008) > #define PCIE_CLIENT_CONF_LANE_NUM(x) HIWORD_UPDATE(0x0030, ENCODE_LANES(x)) > #define PCIE_CLIENT_MODE_RC HIWORD_UPDATE_BIT(0x0040) > -- > 2.46.2 > -- மணிவண்ணன் சதாசிவம்