From: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
To: Damien Le Moal <dlemoal@kernel.org>
Cc: "Lorenzo Pieralisi" <lpieralisi@kernel.org>,
"Kishon Vijay Abraham I" <kishon@kernel.org>,
"Shawn Lin" <shawn.lin@rock-chips.com>,
"Krzysztof Wilczyński" <kw@linux.com>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Heiko Stuebner" <heiko@sntech.de>,
linux-pci@vger.kernel.org, "Rob Herring" <robh@kernel.org>,
"Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>,
"Conor Dooley" <conor+dt@kernel.org>,
devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org,
"Rick Wertenbroek" <rick.wertenbroek@gmail.com>,
"Wilfred Mallawa" <wilfred.mallawa@wdc.com>,
"Niklas Cassel" <cassel@kernel.org>
Subject: Re: [PATCH v3 01/12] PCI: rockchip-ep: Fix address translation unit programming
Date: Thu, 10 Oct 2024 16:06:54 +0530 [thread overview]
Message-ID: <20241010103654.3qmsdtymto55nfl4@thinkpad> (raw)
In-Reply-To: <016bb5a6-5f05-404c-acaf-e0a3ed6fcede@kernel.org>
On Thu, Oct 10, 2024 at 05:41:56PM +0900, Damien Le Moal wrote:
> On 2024/10/10 16:02, Manivannan Sadhasivam wrote:
> > On Mon, Oct 07, 2024 at 01:12:07PM +0900, Damien Le Moal wrote:
> >> The rockchip PCIe endpoint controller handles PCIe transfers addresses
> >> by masking the lower bits of the programmed PCI address and using the
> >> same number of lower bits masked from the CPU address space used for the
> >> mapping. For a PCI mapping of <size> bytes starting from <pci_addr>,
> >> the number of bits masked is the number of address bits changing in the
> >> address range [pci_addr..pci_addr + size - 1].
> >>
> >> However, rockchip_pcie_prog_ep_ob_atu() calculates num_pass_bits only
> >> using the size of the mapping, resulting in an incorrect number of mask
> >> bits depending on the value of the PCI address to map.
> >>
> >> Fix this by introducing the helper function
> >> rockchip_pcie_ep_ob_atu_num_bits() to correctly calculate the number of
> >> mask bits to use to program the address translation unit. The number of
> >> mask bits iscalculated depending on both the PCI address and size of the
> >> mapping, and clamped between 8 and 20 using the macros
> >> ROCKCHIP_PCIE_AT_MIN_NUM_BITS and ROCKCHIP_PCIE_AT_MAX_NUM_BITS.
> >>
> >
> > How did you end up with these clamping values? Are the values (at least MAX
> > applicable to all SoCs)?
> >
> > Btw, it would be helpful if you referenced the TRM and the section that
> > describes the outbound mapping. I'm able to find the reference:
> >
> > Rockchip RK3399 TRM V1.3 Part2, Section 17.5.5.1.1
>
> OK. Will add that.
>
> I really appreciate very much all the reviews you are sending, but given that
> this patch series depends on the series "[PATCH v4 0/7] Improve PCI memory
> mapping API", could we start with that one and get it queued ASAP ?
>
Sure. Sorry for being late btw. Personal errands are eating up the review time.
- Mani
--
மணிவண்ணன் சதாசிவம்
next prev parent reply other threads:[~2024-10-10 10:37 UTC|newest]
Thread overview: 55+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-10-07 4:12 [PATCH v3 00/12] Damien Le Moal
2024-10-07 4:12 ` [PATCH v3 01/12] PCI: rockchip-ep: Fix address translation unit programming Damien Le Moal
2024-10-10 7:02 ` Manivannan Sadhasivam
2024-10-10 8:41 ` Damien Le Moal
2024-10-10 10:36 ` Manivannan Sadhasivam [this message]
2024-10-07 4:12 ` [PATCH v3 02/12] PCI: rockchip-ep: Use a macro to define EP controller .align feature Damien Le Moal
2024-10-10 7:03 ` Manivannan Sadhasivam
2024-10-07 4:12 ` [PATCH v3 03/12] PCI: rockchip-ep: Improve rockchip_pcie_ep_unmap_addr() Damien Le Moal
2024-10-10 7:09 ` Manivannan Sadhasivam
2024-10-11 8:22 ` Damien Le Moal
2024-10-07 4:12 ` [PATCH v3 04/12] PCI: rockchip-ep: Improve rockchip_pcie_ep_map_addr() Damien Le Moal
2024-10-10 7:13 ` Manivannan Sadhasivam
2024-10-12 9:31 ` Manivannan Sadhasivam
2024-10-12 12:02 ` Damien Le Moal
2024-10-12 12:39 ` Manivannan Sadhasivam
2024-10-07 4:12 ` [PATCH v3 05/12] PCI: rockchip-ep: Implement the .map_align() controller operation Damien Le Moal
2024-10-10 2:43 ` kernel test robot
2024-10-10 3:44 ` kernel test robot
2024-10-07 4:12 ` [PATCH v3 06/12] PCI: rockchip-ep: Refactor rockchip_pcie_ep_probe() memory allocations Damien Le Moal
2024-10-10 7:23 ` Manivannan Sadhasivam
2024-10-07 4:12 ` [PATCH v3 07/12] PCI: rockchip-ep: Refactor rockchip_pcie_ep_probe() MSI-X hiding Damien Le Moal
2024-10-10 7:25 ` Manivannan Sadhasivam
2024-10-10 8:09 ` Manivannan Sadhasivam
2024-10-10 8:37 ` Damien Le Moal
2024-10-11 8:30 ` Damien Le Moal
2024-10-12 12:14 ` Manivannan Sadhasivam
2024-10-11 8:25 ` Damien Le Moal
2024-10-12 12:12 ` Manivannan Sadhasivam
2024-10-07 4:12 ` [PATCH v3 08/12] PCI: rockchip-ep: Refactor endpoint link training enable Damien Le Moal
2024-10-10 8:22 ` Manivannan Sadhasivam
2024-10-11 8:45 ` Damien Le Moal
2024-10-07 4:12 ` [PATCH v3 09/12] PCI: rockship-ep: Introduce rockchip_pcie_ep_stop() Damien Le Moal
2024-10-10 8:24 ` Manivannan Sadhasivam
2024-10-07 4:12 ` [PATCH v3 10/12] PCI: rockchip-ep: Improve link training Damien Le Moal
2024-10-10 10:35 ` Manivannan Sadhasivam
2024-10-11 8:55 ` Damien Le Moal
2024-10-12 12:16 ` Manivannan Sadhasivam
2024-10-17 0:52 ` Damien Le Moal
2024-10-07 4:12 ` [PATCH v3 11/12] dt-bindings: pci: rockchip,rk3399-pcie-ep: Add ep-gpios property Damien Le Moal
2024-10-07 6:12 ` Krzysztof Kozlowski
2024-10-07 6:50 ` Damien Le Moal
2024-10-07 6:54 ` Krzysztof Kozlowski
2024-10-07 6:58 ` Damien Le Moal
2024-10-07 7:00 ` Krzysztof Kozlowski
2024-10-07 7:22 ` Damien Le Moal
2024-10-07 7:27 ` Manivannan Sadhasivam
2024-10-07 4:12 ` [PATCH v3 12/12] PCI: rockchip-ep: Handle PERST# signal in endpoint mode Damien Le Moal
2024-10-10 4:35 ` kernel test robot
2024-10-10 10:49 ` Manivannan Sadhasivam
2024-10-11 9:30 ` Damien Le Moal
2024-10-12 12:31 ` Manivannan Sadhasivam
2024-10-15 6:24 ` Damien Le Moal
2024-10-07 4:45 ` [PATCH v3 00/12] Damien Le Moal
2024-10-07 10:02 ` Niklas Cassel
2024-10-07 10:26 ` Damien Le Moal
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