* [PATCH v4 0/3] Add mtk-sd support for MT8196
@ 2024-10-11 2:48 Andy-ld Lu
2024-10-11 2:48 ` [PATCH v4 1/3] mmc: mtk-sd: Add stop_dly_sel and pop_en_cnt to platform data Andy-ld Lu
` (3 more replies)
0 siblings, 4 replies; 6+ messages in thread
From: Andy-ld Lu @ 2024-10-11 2:48 UTC (permalink / raw)
To: ulf.hansson, robh, krzk+dt, matthias.bgg,
angelogioacchino.delregno, wenbin.mei
Cc: linux-mmc, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, Andy-ld Lu
There are some new features for Mediatek SoC MT8196, which include new
command/data transmitting and receiving path (abbreviated as tx/rx), and
two modified register settings.
The driver code has to be adapted to implement the above changes, and the
compatible string 'mediatek,mt8196-mmc' is added to driver and devicetree
bindings.
---
Changes in v4:
- Reorder the first two commits, and update the commit message to explain
why the settings of stop_dly_sel and pop_en_cnt are variant.
Changes in v3:
- Separate the settings for stop_dly_sel and pop_en_cnt to a different
commit;
- Add the original value of stop_dly_sel to the platdata of legacy SoCs,
for unified code setting;
- Change to return if host->top_base is NULL in msdc_new_tx_setting function,
to simplify coding;
- Optimize the location of assignment for 'timing_changed' in msdc_set_mclk
function.
Changes in v2:
- Use compatible string 'mediatek,mt8196-mmc' to replace 'mediatek,msdc-v2';
- Remove the 'mediatek,stop-dly-sel', 'mediatek,pop-en-cnt' and 'mediatek,
prohibit-gate-cg' in devicetree bindings, due to SoC dependent;
- Add 'stop_dly_sel' and 'pop_en_cnt' to the compatiblity structure for
different register settings;
- The SoC's upgraded version would discard the bus design that detect source
clock CG when the CPU access the IP registers, so drop the related control
flow with 'prohibit_gate_cg' flag.
Link to v1:
https://patchwork.kernel.org/patch/13812924
---
Andy-ld Lu (3):
mmc: mtk-sd: Add stop_dly_sel and pop_en_cnt to platform data
mmc: mtk-sd: Add support for MT8196
dt-bindings: mmc: mtk-sd: Add support for MT8196
.../devicetree/bindings/mmc/mtk-sd.yaml | 2 +
drivers/mmc/host/mtk-sd.c | 166 +++++++++++++++---
2 files changed, 147 insertions(+), 21 deletions(-)
--
2.46.0
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v4 1/3] mmc: mtk-sd: Add stop_dly_sel and pop_en_cnt to platform data
2024-10-11 2:48 [PATCH v4 0/3] Add mtk-sd support for MT8196 Andy-ld Lu
@ 2024-10-11 2:48 ` Andy-ld Lu
2024-10-14 7:38 ` AngeloGioacchino Del Regno
2024-10-11 2:48 ` [PATCH v4 2/3] mmc: mtk-sd: Add support for MT8196 Andy-ld Lu
` (2 subsequent siblings)
3 siblings, 1 reply; 6+ messages in thread
From: Andy-ld Lu @ 2024-10-11 2:48 UTC (permalink / raw)
To: ulf.hansson, robh, krzk+dt, matthias.bgg,
angelogioacchino.delregno, wenbin.mei
Cc: linux-mmc, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, Andy-ld Lu
There are modified register settings for STOP_DLY_SEL and POP_EN_CNT
from our next generation SoCs, due to the advanced chip manufacturing
process and the resulting changes in the internal signal timing.
Add two new fields to the compatibility structure to reflect the
modifications. For legacy SoCs, also add the original value of
'stop_dly_sel' to the platform data, for unified code setting.
Signed-off-by: Andy-ld Lu <andy-ld.lu@mediatek.com>
---
drivers/mmc/host/mtk-sd.c | 21 +++++++++++++++++++--
1 file changed, 19 insertions(+), 2 deletions(-)
diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c
index 1efe434391af..aef30bba00b9 100644
--- a/drivers/mmc/host/mtk-sd.c
+++ b/drivers/mmc/host/mtk-sd.c
@@ -248,6 +248,7 @@
#define MSDC_PB2_SUPPORT_64G BIT(1) /* RW */
#define MSDC_PB2_RESPWAIT GENMASK(3, 2) /* RW */
#define MSDC_PB2_RESPSTSENSEL GENMASK(18, 16) /* RW */
+#define MSDC_PB2_POP_EN_CNT GENMASK(23, 20) /* RW */
#define MSDC_PB2_CRCSTSENSEL GENMASK(31, 29) /* RW */
#define MSDC_PAD_TUNE_DATWRDLY GENMASK(4, 0) /* RW */
@@ -403,6 +404,8 @@ struct mtk_mmc_compatible {
bool data_tune;
bool busy_check;
bool stop_clk_fix;
+ u8 stop_dly_sel;
+ u8 pop_en_cnt;
bool enhance_rx;
bool support_64g;
bool use_internal_cd;
@@ -504,6 +507,7 @@ static const struct mtk_mmc_compatible mt2712_compat = {
.data_tune = true,
.busy_check = true,
.stop_clk_fix = true,
+ .stop_dly_sel = 3,
.enhance_rx = true,
.support_64g = true,
};
@@ -517,6 +521,7 @@ static const struct mtk_mmc_compatible mt6779_compat = {
.data_tune = true,
.busy_check = true,
.stop_clk_fix = true,
+ .stop_dly_sel = 3,
.enhance_rx = true,
.support_64g = true,
};
@@ -556,6 +561,7 @@ static const struct mtk_mmc_compatible mt7622_compat = {
.data_tune = true,
.busy_check = true,
.stop_clk_fix = true,
+ .stop_dly_sel = 3,
.enhance_rx = true,
.support_64g = false,
};
@@ -569,6 +575,7 @@ static const struct mtk_mmc_compatible mt7986_compat = {
.data_tune = true,
.busy_check = true,
.stop_clk_fix = true,
+ .stop_dly_sel = 3,
.enhance_rx = true,
.support_64g = true,
};
@@ -608,6 +615,7 @@ static const struct mtk_mmc_compatible mt8183_compat = {
.data_tune = true,
.busy_check = true,
.stop_clk_fix = true,
+ .stop_dly_sel = 3,
.enhance_rx = true,
.support_64g = true,
};
@@ -621,6 +629,7 @@ static const struct mtk_mmc_compatible mt8516_compat = {
.data_tune = true,
.busy_check = true,
.stop_clk_fix = true,
+ .stop_dly_sel = 3,
};
static const struct of_device_id msdc_of_ids[] = {
@@ -1767,8 +1776,16 @@ static void msdc_init_hw(struct msdc_host *host)
sdr_set_bits(host->base + EMMC50_CFG0, EMMC50_CFG_CFCSTS_SEL);
if (host->dev_comp->stop_clk_fix) {
- sdr_set_field(host->base + MSDC_PATCH_BIT1,
- MSDC_PATCH_BIT1_STOP_DLY, 3);
+ if (host->dev_comp->stop_dly_sel)
+ sdr_set_field(host->base + MSDC_PATCH_BIT1,
+ MSDC_PATCH_BIT1_STOP_DLY,
+ host->dev_comp->stop_dly_sel);
+
+ if (host->dev_comp->pop_en_cnt)
+ sdr_set_field(host->base + MSDC_PATCH_BIT2,
+ MSDC_PB2_POP_EN_CNT,
+ host->dev_comp->pop_en_cnt);
+
sdr_clr_bits(host->base + SDC_FIFO_CFG,
SDC_FIFO_CFG_WRVALIDSEL);
sdr_clr_bits(host->base + SDC_FIFO_CFG,
--
2.46.0
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v4 2/3] mmc: mtk-sd: Add support for MT8196
2024-10-11 2:48 [PATCH v4 0/3] Add mtk-sd support for MT8196 Andy-ld Lu
2024-10-11 2:48 ` [PATCH v4 1/3] mmc: mtk-sd: Add stop_dly_sel and pop_en_cnt to platform data Andy-ld Lu
@ 2024-10-11 2:48 ` Andy-ld Lu
2024-10-11 2:48 ` [PATCH v4 3/3] dt-bindings: " Andy-ld Lu
2024-10-25 14:51 ` [PATCH v4 0/3] Add mtk-sd " Ulf Hansson
3 siblings, 0 replies; 6+ messages in thread
From: Andy-ld Lu @ 2024-10-11 2:48 UTC (permalink / raw)
To: ulf.hansson, robh, krzk+dt, matthias.bgg,
angelogioacchino.delregno, wenbin.mei
Cc: linux-mmc, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, Andy-ld Lu
Mediatek SoC MT8196 features a new design for tx/rx path. The new tx
path incorporates register settings that are closely associated with
bus timing. And the difference between new rx path and older versions
is the usage of distinct register bits when setting the data sampling
edge as part of the tuning process.
Besides, the register settings for STOP_DLY_SEL and POP_EN_CNT are
different from previous SoCs.
For the changes mentioned in relation to the MT8196, the new compatible
string 'mediatek,mt8196-mmc' is introduced. This is to accommodate
different settings and workflows specific to the MT8196.
Signed-off-by: Andy-ld Lu <andy-ld.lu@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
drivers/mmc/host/mtk-sd.c | 145 +++++++++++++++++++++++++++++++++-----
1 file changed, 126 insertions(+), 19 deletions(-)
diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c
index aef30bba00b9..4c239a4cf8d9 100644
--- a/drivers/mmc/host/mtk-sd.c
+++ b/drivers/mmc/host/mtk-sd.c
@@ -66,6 +66,7 @@
#define SDC_RESP3 0x4c
#define SDC_BLK_NUM 0x50
#define SDC_ADV_CFG0 0x64
+#define MSDC_NEW_RX_CFG 0x68
#define EMMC_IOCON 0x7c
#define SDC_ACMD_RESP 0x80
#define DMA_SA_H4BIT 0x8c
@@ -92,6 +93,7 @@
#define EMMC_TOP_CONTROL 0x00
#define EMMC_TOP_CMD 0x04
#define EMMC50_PAD_DS_TUNE 0x0c
+#define LOOP_TEST_CONTROL 0x30
/*--------------------------------------------------------------------------*/
/* Register Mask */
@@ -203,9 +205,13 @@
#define SDC_STS_CMDBUSY BIT(1) /* RW */
#define SDC_STS_SWR_COMPL BIT(31) /* RW */
-#define SDC_DAT1_IRQ_TRIGGER BIT(19) /* RW */
/* SDC_ADV_CFG0 mask */
+#define SDC_DAT1_IRQ_TRIGGER BIT(19) /* RW */
#define SDC_RX_ENHANCE_EN BIT(20) /* RW */
+#define SDC_NEW_TX_EN BIT(31) /* RW */
+
+/* MSDC_NEW_RX_CFG mask */
+#define MSDC_NEW_RX_PATH_SEL BIT(0) /* RW */
/* DMA_SA_H4BIT mask */
#define DMA_ADDR_HIGH_4BIT GENMASK(3, 0) /* RW */
@@ -227,6 +233,7 @@
/* MSDC_PATCH_BIT mask */
#define MSDC_PATCH_BIT_ODDSUPP BIT(1) /* RW */
+#define MSDC_PATCH_BIT_RD_DAT_SEL BIT(3) /* RW */
#define MSDC_INT_DAT_LATCH_CK_SEL GENMASK(9, 7)
#define MSDC_CKGEN_MSDC_DLY_SEL GENMASK(14, 10)
#define MSDC_PATCH_BIT_IODSSEL BIT(16) /* RW */
@@ -249,6 +256,7 @@
#define MSDC_PB2_RESPWAIT GENMASK(3, 2) /* RW */
#define MSDC_PB2_RESPSTSENSEL GENMASK(18, 16) /* RW */
#define MSDC_PB2_POP_EN_CNT GENMASK(23, 20) /* RW */
+#define MSDC_PB2_CFGCRCSTSEDGE BIT(25) /* RW */
#define MSDC_PB2_CRCSTSENSEL GENMASK(31, 29) /* RW */
#define MSDC_PAD_TUNE_DATWRDLY GENMASK(4, 0) /* RW */
@@ -313,6 +321,12 @@
#define PAD_DS_DLY1 GENMASK(14, 10) /* RW */
#define PAD_DS_DLY3 GENMASK(4, 0) /* RW */
+/* LOOP_TEST_CONTROL mask */
+#define TEST_LOOP_DSCLK_MUX_SEL BIT(0) /* RW */
+#define TEST_LOOP_LATCH_MUX_SEL BIT(1) /* RW */
+#define LOOP_EN_SEL_CLK BIT(20) /* RW */
+#define TEST_HS400_CMD_LOOP_MUX_SEL BIT(31) /* RW */
+
#define REQ_CMD_EIO BIT(0)
#define REQ_CMD_TMO BIT(1)
#define REQ_DAT_ERR BIT(2)
@@ -393,6 +407,7 @@ struct msdc_save_para {
u32 emmc_top_control;
u32 emmc_top_cmd;
u32 emmc50_pad_ds_tune;
+ u32 loop_test_control;
};
struct mtk_mmc_compatible {
@@ -409,6 +424,8 @@ struct mtk_mmc_compatible {
bool enhance_rx;
bool support_64g;
bool use_internal_cd;
+ bool support_new_tx;
+ bool support_new_rx;
};
struct msdc_tune_para {
@@ -632,6 +649,23 @@ static const struct mtk_mmc_compatible mt8516_compat = {
.stop_dly_sel = 3,
};
+static const struct mtk_mmc_compatible mt8196_compat = {
+ .clk_div_bits = 12,
+ .recheck_sdio_irq = false,
+ .hs400_tune = false,
+ .pad_tune_reg = MSDC_PAD_TUNE0,
+ .async_fifo = true,
+ .data_tune = true,
+ .busy_check = true,
+ .stop_clk_fix = true,
+ .stop_dly_sel = 1,
+ .pop_en_cnt = 2,
+ .enhance_rx = true,
+ .support_64g = true,
+ .support_new_tx = true,
+ .support_new_rx = true,
+};
+
static const struct of_device_id msdc_of_ids[] = {
{ .compatible = "mediatek,mt2701-mmc", .data = &mt2701_compat},
{ .compatible = "mediatek,mt2712-mmc", .data = &mt2712_compat},
@@ -643,6 +677,7 @@ static const struct of_device_id msdc_of_ids[] = {
{ .compatible = "mediatek,mt8135-mmc", .data = &mt8135_compat},
{ .compatible = "mediatek,mt8173-mmc", .data = &mt8173_compat},
{ .compatible = "mediatek,mt8183-mmc", .data = &mt8183_compat},
+ { .compatible = "mediatek,mt8196-mmc", .data = &mt8196_compat},
{ .compatible = "mediatek,mt8516-mmc", .data = &mt8516_compat},
{}
@@ -883,6 +918,41 @@ static int msdc_ungate_clock(struct msdc_host *host)
(val & MSDC_CFG_CKSTB), 1, 20000);
}
+static void msdc_new_tx_setting(struct msdc_host *host)
+{
+ if (!host->top_base)
+ return;
+
+ sdr_set_bits(host->top_base + LOOP_TEST_CONTROL,
+ TEST_LOOP_DSCLK_MUX_SEL);
+ sdr_set_bits(host->top_base + LOOP_TEST_CONTROL,
+ TEST_LOOP_LATCH_MUX_SEL);
+ sdr_clr_bits(host->top_base + LOOP_TEST_CONTROL,
+ TEST_HS400_CMD_LOOP_MUX_SEL);
+
+ switch (host->timing) {
+ case MMC_TIMING_LEGACY:
+ case MMC_TIMING_MMC_HS:
+ case MMC_TIMING_SD_HS:
+ case MMC_TIMING_UHS_SDR12:
+ case MMC_TIMING_UHS_SDR25:
+ case MMC_TIMING_UHS_DDR50:
+ case MMC_TIMING_MMC_DDR52:
+ sdr_clr_bits(host->top_base + LOOP_TEST_CONTROL,
+ LOOP_EN_SEL_CLK);
+ break;
+ case MMC_TIMING_UHS_SDR50:
+ case MMC_TIMING_UHS_SDR104:
+ case MMC_TIMING_MMC_HS200:
+ case MMC_TIMING_MMC_HS400:
+ sdr_set_bits(host->top_base + LOOP_TEST_CONTROL,
+ LOOP_EN_SEL_CLK);
+ break;
+ default:
+ break;
+ }
+}
+
static void msdc_set_mclk(struct msdc_host *host, unsigned char timing, u32 hz)
{
struct mmc_host *mmc = mmc_from_priv(host);
@@ -892,6 +962,7 @@ static void msdc_set_mclk(struct msdc_host *host, unsigned char timing, u32 hz)
u32 sclk;
u32 tune_reg = host->dev_comp->pad_tune_reg;
u32 val;
+ bool timing_changed;
if (!hz) {
dev_dbg(host->dev, "set mclk to 0\n");
@@ -901,6 +972,11 @@ static void msdc_set_mclk(struct msdc_host *host, unsigned char timing, u32 hz)
return;
}
+ if (host->timing != timing)
+ timing_changed = true;
+ else
+ timing_changed = false;
+
flags = readl(host->base + MSDC_INTEN);
sdr_clr_bits(host->base + MSDC_INTEN, flags);
if (host->dev_comp->clk_div_bits == 8)
@@ -1007,6 +1083,9 @@ static void msdc_set_mclk(struct msdc_host *host, unsigned char timing, u32 hz)
sdr_set_field(host->base + tune_reg,
MSDC_PAD_TUNE_CMDRRDLY,
host->hs400_cmd_int_delay);
+ if (host->dev_comp->support_new_tx && timing_changed)
+ msdc_new_tx_setting(host);
+
dev_dbg(host->dev, "sclk: %d, timing: %d\n", mmc->actual_clock,
timing);
}
@@ -1738,6 +1817,17 @@ static void msdc_init_hw(struct msdc_host *host)
reset_control_deassert(host->reset);
}
+ /* New tx/rx enable bit need to be 0->1 for hardware check */
+ if (host->dev_comp->support_new_tx) {
+ sdr_clr_bits(host->base + SDC_ADV_CFG0, SDC_NEW_TX_EN);
+ sdr_set_bits(host->base + SDC_ADV_CFG0, SDC_NEW_TX_EN);
+ msdc_new_tx_setting(host);
+ }
+ if (host->dev_comp->support_new_rx) {
+ sdr_clr_bits(host->base + MSDC_NEW_RX_CFG, MSDC_NEW_RX_PATH_SEL);
+ sdr_set_bits(host->base + MSDC_NEW_RX_CFG, MSDC_NEW_RX_PATH_SEL);
+ }
+
/* Configure to MMC/SD mode, clock free running */
sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_MODE | MSDC_CFG_CKPDN);
@@ -2097,6 +2187,19 @@ static inline void msdc_set_data_delay(struct msdc_host *host, u32 value)
}
}
+static inline void msdc_set_data_sample_edge(struct msdc_host *host, bool rising)
+{
+ u32 value = rising ? 0 : 1;
+
+ if (host->dev_comp->support_new_rx) {
+ sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_PATCH_BIT_RD_DAT_SEL, value);
+ sdr_set_field(host->base + MSDC_PATCH_BIT2, MSDC_PB2_CFGCRCSTSEDGE, value);
+ } else {
+ sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_DSPL, value);
+ sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL, value);
+ }
+}
+
static int msdc_tune_response(struct mmc_host *mmc, u32 opcode)
{
struct msdc_host *host = mmc_priv(mmc);
@@ -2252,8 +2355,7 @@ static int msdc_tune_data(struct mmc_host *mmc, u32 opcode)
sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL,
host->latch_ck);
- sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
- sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
+ msdc_set_data_sample_edge(host, true);
for (i = 0; i < host->tuning_step; i++) {
msdc_set_data_delay(host, i);
ret = mmc_send_tuning(mmc, opcode, NULL);
@@ -2266,8 +2368,7 @@ static int msdc_tune_data(struct mmc_host *mmc, u32 opcode)
(final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4))
goto skip_fall;
- sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
- sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
+ msdc_set_data_sample_edge(host, false);
for (i = 0; i < host->tuning_step; i++) {
msdc_set_data_delay(host, i);
ret = mmc_send_tuning(mmc, opcode, NULL);
@@ -2279,12 +2380,10 @@ static int msdc_tune_data(struct mmc_host *mmc, u32 opcode)
skip_fall:
final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen);
if (final_maxlen == final_rise_delay.maxlen) {
- sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
- sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
+ msdc_set_data_sample_edge(host, true);
final_delay = final_rise_delay.final_phase;
} else {
- sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
- sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
+ msdc_set_data_sample_edge(host, false);
final_delay = final_fall_delay.final_phase;
}
msdc_set_data_delay(host, final_delay);
@@ -2309,8 +2408,7 @@ static int msdc_tune_together(struct mmc_host *mmc, u32 opcode)
host->latch_ck);
sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
- sdr_clr_bits(host->base + MSDC_IOCON,
- MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
+ msdc_set_data_sample_edge(host, true);
for (i = 0; i < host->tuning_step; i++) {
msdc_set_cmd_delay(host, i);
msdc_set_data_delay(host, i);
@@ -2325,8 +2423,7 @@ static int msdc_tune_together(struct mmc_host *mmc, u32 opcode)
goto skip_fall;
sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
- sdr_set_bits(host->base + MSDC_IOCON,
- MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
+ msdc_set_data_sample_edge(host, false);
for (i = 0; i < host->tuning_step; i++) {
msdc_set_cmd_delay(host, i);
msdc_set_data_delay(host, i);
@@ -2340,13 +2437,11 @@ static int msdc_tune_together(struct mmc_host *mmc, u32 opcode)
final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen);
if (final_maxlen == final_rise_delay.maxlen) {
sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
- sdr_clr_bits(host->base + MSDC_IOCON,
- MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
+ msdc_set_data_sample_edge(host, true);
final_delay = final_rise_delay.final_phase;
} else {
sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
- sdr_set_bits(host->base + MSDC_IOCON,
- MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
+ msdc_set_data_sample_edge(host, false);
final_delay = final_fall_delay.final_phase;
}
@@ -2366,8 +2461,7 @@ static int msdc_execute_tuning(struct mmc_host *mmc, u32 opcode)
if (host->dev_comp->data_tune && host->dev_comp->async_fifo) {
ret = msdc_tune_together(mmc, opcode);
if (host->hs400_mode) {
- sdr_clr_bits(host->base + MSDC_IOCON,
- MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
+ msdc_set_data_sample_edge(host, true);
msdc_set_data_delay(host, 0);
}
goto tune_done;
@@ -3030,6 +3124,8 @@ static void msdc_save_reg(struct msdc_host *host)
readl(host->top_base + EMMC_TOP_CMD);
host->save_para.emmc50_pad_ds_tune =
readl(host->top_base + EMMC50_PAD_DS_TUNE);
+ host->save_para.loop_test_control =
+ readl(host->top_base + LOOP_TEST_CONTROL);
} else {
host->save_para.pad_tune = readl(host->base + tune_reg);
}
@@ -3040,6 +3136,15 @@ static void msdc_restore_reg(struct msdc_host *host)
struct mmc_host *mmc = mmc_from_priv(host);
u32 tune_reg = host->dev_comp->pad_tune_reg;
+ if (host->dev_comp->support_new_tx) {
+ sdr_clr_bits(host->base + SDC_ADV_CFG0, SDC_NEW_TX_EN);
+ sdr_set_bits(host->base + SDC_ADV_CFG0, SDC_NEW_TX_EN);
+ }
+ if (host->dev_comp->support_new_rx) {
+ sdr_clr_bits(host->base + MSDC_NEW_RX_CFG, MSDC_NEW_RX_PATH_SEL);
+ sdr_set_bits(host->base + MSDC_NEW_RX_CFG, MSDC_NEW_RX_PATH_SEL);
+ }
+
writel(host->save_para.msdc_cfg, host->base + MSDC_CFG);
writel(host->save_para.iocon, host->base + MSDC_IOCON);
writel(host->save_para.sdc_cfg, host->base + SDC_CFG);
@@ -3058,6 +3163,8 @@ static void msdc_restore_reg(struct msdc_host *host)
host->top_base + EMMC_TOP_CMD);
writel(host->save_para.emmc50_pad_ds_tune,
host->top_base + EMMC50_PAD_DS_TUNE);
+ writel(host->save_para.loop_test_control,
+ host->top_base + LOOP_TEST_CONTROL);
} else {
writel(host->save_para.pad_tune, host->base + tune_reg);
}
--
2.46.0
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v4 3/3] dt-bindings: mmc: mtk-sd: Add support for MT8196
2024-10-11 2:48 [PATCH v4 0/3] Add mtk-sd support for MT8196 Andy-ld Lu
2024-10-11 2:48 ` [PATCH v4 1/3] mmc: mtk-sd: Add stop_dly_sel and pop_en_cnt to platform data Andy-ld Lu
2024-10-11 2:48 ` [PATCH v4 2/3] mmc: mtk-sd: Add support for MT8196 Andy-ld Lu
@ 2024-10-11 2:48 ` Andy-ld Lu
2024-10-25 14:51 ` [PATCH v4 0/3] Add mtk-sd " Ulf Hansson
3 siblings, 0 replies; 6+ messages in thread
From: Andy-ld Lu @ 2024-10-11 2:48 UTC (permalink / raw)
To: ulf.hansson, robh, krzk+dt, matthias.bgg,
angelogioacchino.delregno, wenbin.mei
Cc: linux-mmc, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, Andy-ld Lu, Krzysztof Kozlowski
Extend the devicetree bindings to include the MT8196 mmc controller,
new tx/rx would be supported from MT8196, and the register settings
of STOP_DLY_SEL and POP_EN_CNT would also be variant.
Signed-off-by: Andy-ld Lu <andy-ld.lu@mediatek.com>
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
Documentation/devicetree/bindings/mmc/mtk-sd.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
index c532ec92d2d9..9281a0326891 100644
--- a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
+++ b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
@@ -24,6 +24,7 @@ properties:
- mediatek,mt8135-mmc
- mediatek,mt8173-mmc
- mediatek,mt8183-mmc
+ - mediatek,mt8196-mmc
- mediatek,mt8516-mmc
- items:
- const: mediatek,mt7623-mmc
@@ -190,6 +191,7 @@ allOf:
- mediatek,mt8186-mmc
- mediatek,mt8188-mmc
- mediatek,mt8195-mmc
+ - mediatek,mt8196-mmc
- mediatek,mt8516-mmc
then:
properties:
--
2.46.0
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH v4 1/3] mmc: mtk-sd: Add stop_dly_sel and pop_en_cnt to platform data
2024-10-11 2:48 ` [PATCH v4 1/3] mmc: mtk-sd: Add stop_dly_sel and pop_en_cnt to platform data Andy-ld Lu
@ 2024-10-14 7:38 ` AngeloGioacchino Del Regno
0 siblings, 0 replies; 6+ messages in thread
From: AngeloGioacchino Del Regno @ 2024-10-14 7:38 UTC (permalink / raw)
To: Andy-ld Lu, ulf.hansson, robh, krzk+dt, matthias.bgg, wenbin.mei
Cc: linux-mmc, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek
Il 11/10/24 04:48, Andy-ld Lu ha scritto:
> There are modified register settings for STOP_DLY_SEL and POP_EN_CNT
> from our next generation SoCs, due to the advanced chip manufacturing
> process and the resulting changes in the internal signal timing.
>
> Add two new fields to the compatibility structure to reflect the
> modifications. For legacy SoCs, also add the original value of
> 'stop_dly_sel' to the platform data, for unified code setting.
>
> Signed-off-by: Andy-ld Lu <andy-ld.lu@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v4 0/3] Add mtk-sd support for MT8196
2024-10-11 2:48 [PATCH v4 0/3] Add mtk-sd support for MT8196 Andy-ld Lu
` (2 preceding siblings ...)
2024-10-11 2:48 ` [PATCH v4 3/3] dt-bindings: " Andy-ld Lu
@ 2024-10-25 14:51 ` Ulf Hansson
3 siblings, 0 replies; 6+ messages in thread
From: Ulf Hansson @ 2024-10-25 14:51 UTC (permalink / raw)
To: Andy-ld Lu
Cc: robh, krzk+dt, matthias.bgg, angelogioacchino.delregno,
wenbin.mei, linux-mmc, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek
On Fri, 11 Oct 2024 at 04:49, Andy-ld Lu <andy-ld.lu@mediatek.com> wrote:
>
> There are some new features for Mediatek SoC MT8196, which include new
> command/data transmitting and receiving path (abbreviated as tx/rx), and
> two modified register settings.
>
> The driver code has to be adapted to implement the above changes, and the
> compatible string 'mediatek,mt8196-mmc' is added to driver and devicetree
> bindings.
>
> ---
> Changes in v4:
> - Reorder the first two commits, and update the commit message to explain
> why the settings of stop_dly_sel and pop_en_cnt are variant.
The series applied for next, thanks!
Note that, I have put patch3 as the first one. Updates of the DT
bindings should come prior to the driver updates that make use of the
them.
Kind regards
Uffe
>
> Changes in v3:
> - Separate the settings for stop_dly_sel and pop_en_cnt to a different
> commit;
> - Add the original value of stop_dly_sel to the platdata of legacy SoCs,
> for unified code setting;
> - Change to return if host->top_base is NULL in msdc_new_tx_setting function,
> to simplify coding;
> - Optimize the location of assignment for 'timing_changed' in msdc_set_mclk
> function.
>
> Changes in v2:
> - Use compatible string 'mediatek,mt8196-mmc' to replace 'mediatek,msdc-v2';
> - Remove the 'mediatek,stop-dly-sel', 'mediatek,pop-en-cnt' and 'mediatek,
> prohibit-gate-cg' in devicetree bindings, due to SoC dependent;
> - Add 'stop_dly_sel' and 'pop_en_cnt' to the compatiblity structure for
> different register settings;
> - The SoC's upgraded version would discard the bus design that detect source
> clock CG when the CPU access the IP registers, so drop the related control
> flow with 'prohibit_gate_cg' flag.
>
> Link to v1:
> https://patchwork.kernel.org/patch/13812924
>
> ---
> Andy-ld Lu (3):
> mmc: mtk-sd: Add stop_dly_sel and pop_en_cnt to platform data
> mmc: mtk-sd: Add support for MT8196
> dt-bindings: mmc: mtk-sd: Add support for MT8196
>
> .../devicetree/bindings/mmc/mtk-sd.yaml | 2 +
> drivers/mmc/host/mtk-sd.c | 166 +++++++++++++++---
> 2 files changed, 147 insertions(+), 21 deletions(-)
>
> --
> 2.46.0
>
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2024-10-25 14:51 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2024-10-11 2:48 [PATCH v4 0/3] Add mtk-sd support for MT8196 Andy-ld Lu
2024-10-11 2:48 ` [PATCH v4 1/3] mmc: mtk-sd: Add stop_dly_sel and pop_en_cnt to platform data Andy-ld Lu
2024-10-14 7:38 ` AngeloGioacchino Del Regno
2024-10-11 2:48 ` [PATCH v4 2/3] mmc: mtk-sd: Add support for MT8196 Andy-ld Lu
2024-10-11 2:48 ` [PATCH v4 3/3] dt-bindings: " Andy-ld Lu
2024-10-25 14:51 ` [PATCH v4 0/3] Add mtk-sd " Ulf Hansson
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