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AJvYcCU6ZfusIuOPsFrP7H7GRZ9h4mhiOkobwvw/4SQGSTDQJ83UEUeiHVc19Cw2I8PPXe034NY7e4T8xHzC@vger.kernel.org X-Gm-Message-State: AOJu0Yxe0mf3UAIi9If5j8LMO1yaNQKsGeP64G2uFil9RDjdtS95uCI6 svA/ZQmZq/xzFOEeofWwuD/tDRJwG0OUJzGeoKf3oOzvagL0QlV8+8vB9Sl1eA== X-Google-Smtp-Source: AGHT+IHxOL7Syd/cGt2BqV95e4Kdw1tNZz3+9j9/FIOE1zxN0smZKiOoLQJ5RmgWDoO3/JTFDgCGEA== X-Received: by 2002:a05:6a21:3998:b0:1d7:1277:8d12 with SMTP id adf61e73a8af0-1d8bcf5c061mr6324102637.29.1728707030426; Fri, 11 Oct 2024 21:23:50 -0700 (PDT) Received: from thinkpad ([220.158.156.122]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-71e3ba69fdasm1926423b3a.205.2024.10.11.21.23.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Oct 2024 21:23:50 -0700 (PDT) Date: Sat, 12 Oct 2024 09:53:42 +0530 From: Manivannan Sadhasivam To: Qiang Yu Cc: vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, andersson@kernel.org, konradybcio@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, abel.vesa@linaro.org, quic_msarkar@quicinc.com, quic_devipriy@quicinc.com, dmitry.baryshkov@linaro.org, kw@linux.com, lpieralisi@kernel.org, neil.armstrong@linaro.org, linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org Subject: Re: [PATCH v6 6/8] PCI: qcom: Fix the ops for SC8280X family SoC Message-ID: <20241012041734.y6nwumij27dkbcra@thinkpad> References: <20241011104142.1181773-1-quic_qianyu@quicinc.com> <20241011104142.1181773-7-quic_qianyu@quicinc.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20241011104142.1181773-7-quic_qianyu@quicinc.com> On Fri, Oct 11, 2024 at 03:41:40AM -0700, Qiang Yu wrote: > On SC8280X family SoC, PCIe controllers are connected to SMMUv3, hence > they don't need the config_sid() callback in ops_1_9_0 struct. Fix it by > introducing a new ops struct, namely ops_1_21_0, so that BDF2SID mapping '...namely ops_1_21_0 which is same as ops_1_9_0 without config_sid() callback' > won't be configured during init. > > Fixes: d1997c987814 ("PCI: qcom: Disable ASPM L0s for sc8280xp, sa8540p and sa8295p") > Signed-off-by: Qiang Yu Reviewed-by: Manivannan Sadhasivam - Mani > --- > drivers/pci/controller/dwc/pcie-qcom.c | 12 +++++++++++- > 1 file changed, 11 insertions(+), 1 deletion(-) > > diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c > index 88a98be930e3..468bd4242e61 100644 > --- a/drivers/pci/controller/dwc/pcie-qcom.c > +++ b/drivers/pci/controller/dwc/pcie-qcom.c > @@ -1367,6 +1367,16 @@ static const struct qcom_pcie_ops ops_2_9_0 = { > .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable, > }; > > +/* Qcom IP rev.: 1.21.0 */ > +static const struct qcom_pcie_ops ops_1_21_0 = { > + .get_resources = qcom_pcie_get_resources_2_7_0, > + .init = qcom_pcie_init_2_7_0, > + .post_init = qcom_pcie_post_init_2_7_0, > + .host_post_init = qcom_pcie_host_post_init_2_7_0, > + .deinit = qcom_pcie_deinit_2_7_0, > + .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable, > +}; > + > static const struct qcom_pcie_cfg cfg_1_0_0 = { > .ops = &ops_1_0_0, > }; > @@ -1405,7 +1415,7 @@ static const struct qcom_pcie_cfg cfg_2_9_0 = { > }; > > static const struct qcom_pcie_cfg cfg_sc8280xp = { > - .ops = &ops_1_9_0, > + .ops = &ops_1_21_0, > .no_l0s = true, > }; > > -- > 2.34.1 > -- மணிவண்ணன் சதாசிவம்