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AJvYcCWIH796EsbnAQlwjzhaGP92rFEi6JP0XZyGTGBjYN4ApbsP+1IqttiRtuiSgdmkkfGQq+OBZ4K4dmpw@vger.kernel.org X-Gm-Message-State: AOJu0YxROzBfAo0fhj+DbCrdoZwiqZRALpTsuiQsimnMVxlilgVuMusI uSa+gASpeNk4cHWxYK/m3i/eOOl/N6Ak8y4DVW31txUMfr1vY03hMerRBDWoDg== X-Google-Smtp-Source: AGHT+IHqiyyz1xhjY6vqhIqY84FxPaW6G2o/VAwjL/1LFjW/xaek+9WCg+PZY5ymNnouaWkyvQGCag== X-Received: by 2002:a17:90b:893:b0:2e0:a47a:5eb0 with SMTP id 98e67ed59e1d1-2e2f0da8051mr5652417a91.38.1728711406131; Fri, 11 Oct 2024 22:36:46 -0700 (PDT) Received: from thinkpad ([220.158.156.122]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2e2a36417afsm6683894a91.0.2024.10.11.22.36.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Oct 2024 22:36:45 -0700 (PDT) Date: Sat, 12 Oct 2024 11:06:37 +0530 From: Manivannan Sadhasivam To: Qiang Yu Cc: vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, andersson@kernel.org, konradybcio@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, abel.vesa@linaro.org, quic_msarkar@quicinc.com, quic_devipriy@quicinc.com, dmitry.baryshkov@linaro.org, kw@linux.com, lpieralisi@kernel.org, neil.armstrong@linaro.org, linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org Subject: Re: [PATCH v6 7/8] PCI: qcom: Fix the cfg for X1E80100 SoC Message-ID: <20241012053637.cu2eyle6d7gbqsth@thinkpad> References: <20241011104142.1181773-1-quic_qianyu@quicinc.com> <20241011104142.1181773-8-quic_qianyu@quicinc.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20241011104142.1181773-8-quic_qianyu@quicinc.com> On Fri, Oct 11, 2024 at 03:41:41AM -0700, Qiang Yu wrote: > Currently, the cfg_1_9_0 which is being used for X1E80100 has config_sid > callback in its ops and doesn't disable ASPM L0s. However, as same as > SC8280X, PCIe controllers on X1E80100 are connected to SMMUv3 and it is "...connected to SMMUv3, hence doesn't need config_sid() callback" > recommended to disable ASPM L0s. Hence reuse cfg_sc8280xp for X1E80100. "...and hardware team has recommended to disable L0s as it is broken in the controller." > > Fixes: 6d0c39324c5f ("PCI: qcom: Add X1E80100 PCIe support") > Signed-off-by: Qiang Yu Reviewed-by: Manivannan Sadhasivam We need to backport this patch to stable to fix the L0s handling. But we don't need the previous patch as even without that cfg_sc8280xp disables L0s. - Mani > --- > drivers/pci/controller/dwc/pcie-qcom.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c > index 468bd4242e61..c533e6024ba2 100644 > --- a/drivers/pci/controller/dwc/pcie-qcom.c > +++ b/drivers/pci/controller/dwc/pcie-qcom.c > @@ -1847,7 +1847,7 @@ static const struct of_device_id qcom_pcie_match[] = { > { .compatible = "qcom,pcie-sm8450-pcie0", .data = &cfg_1_9_0 }, > { .compatible = "qcom,pcie-sm8450-pcie1", .data = &cfg_1_9_0 }, > { .compatible = "qcom,pcie-sm8550", .data = &cfg_1_9_0 }, > - { .compatible = "qcom,pcie-x1e80100", .data = &cfg_1_9_0 }, > + { .compatible = "qcom,pcie-x1e80100", .data = &cfg_sc8280xp }, > { } > }; > > -- > 2.34.1 > -- மணிவண்ணன் சதாசிவம்