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AJvYcCUss7dqpeUTPowc8V1tCWqiKwDIhbfYR6V6cNevzKELheD2CsDf51YuZ8gafU2xrmsID0iL7CZHgtUl@vger.kernel.org X-Gm-Message-State: AOJu0YzYNS3LrUSiQu400TsMkGttOCSIwTYEQ5FbML6qMaf5eaLaJF0/ av4WDKTMuX6FAJBnAD5gGz44NPJxm2M2SRPU8mvQe8wBBLsc9b079Fk2LXIhOQ== X-Google-Smtp-Source: AGHT+IFJFAKq8AvKr5WqJJluQSblJRPi1x8ZqEJtRUpmaq30Rs5xjtclmV9IFrQu3SO8OQr5mniMDQ== X-Received: by 2002:a05:6a21:168e:b0:1d7:7ea:2f36 with SMTP id adf61e73a8af0-1d8bcefde33mr8009237637.4.1728735390374; Sat, 12 Oct 2024 05:16:30 -0700 (PDT) Received: from thinkpad ([220.158.156.122]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-71e4dbad815sm1142523b3a.175.2024.10.12.05.16.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 12 Oct 2024 05:16:29 -0700 (PDT) Date: Sat, 12 Oct 2024 17:46:22 +0530 From: Manivannan Sadhasivam To: Damien Le Moal Cc: Lorenzo Pieralisi , Kishon Vijay Abraham I , Shawn Lin , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Bjorn Helgaas , Heiko Stuebner , linux-pci@vger.kernel.org, Rob Herring , Krzysztof Kozlowski , Conor Dooley , devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org, Rick Wertenbroek , Wilfred Mallawa , Niklas Cassel Subject: Re: [PATCH v3 10/12] PCI: rockchip-ep: Improve link training Message-ID: <20241012121622.owkg5geqp5jqtjod@thinkpad> References: <20241007041218.157516-1-dlemoal@kernel.org> <20241007041218.157516-11-dlemoal@kernel.org> <20241010103550.elwd2k35t4k4cypu@thinkpad> <84efa346-c1de-44d5-8b27-2481043e9102@kernel.org> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <84efa346-c1de-44d5-8b27-2481043e9102@kernel.org> On Fri, Oct 11, 2024 at 05:55:25PM +0900, Damien Le Moal wrote: > On 10/10/24 19:35, Manivannan Sadhasivam wrote: > >> +static void rockchip_pcie_ep_link_training(struct work_struct *work) > >> +{ > >> + struct rockchip_pcie_ep *ep = > >> + container_of(work, struct rockchip_pcie_ep, link_training.work); > >> + struct rockchip_pcie *rockchip = &ep->rockchip; > >> + struct device *dev = rockchip->dev; > >> + u32 val; > >> + int ret; > >> + > >> + /* Enable Gen1 training and wait for its completion */ > >> + ret = readl_poll_timeout(rockchip->apb_base + PCIE_CORE_CTRL, > >> + val, PCIE_LINK_TRAINING_DONE(val), 50, > >> + LINK_TRAIN_TIMEOUT); > >> + if (ret) > >> + goto again; > >> + > >> + /* Make sure that the link is up */ > >> + ret = readl_poll_timeout(rockchip->apb_base + PCIE_CLIENT_BASIC_STATUS1, > >> + val, PCIE_LINK_UP(val), 50, > >> + LINK_TRAIN_TIMEOUT); > >> + if (ret) > >> + goto again; > >> + > >> + /* Check the current speed */ > >> + val = rockchip_pcie_read(rockchip, PCIE_CORE_CTRL); > >> + if (!PCIE_LINK_IS_GEN2(val) && rockchip->link_gen == 2) { > > > > PCIE_LINK_IS_GEN2()? > > This is defined in drivers/pci/controller/pcie-rockchip.h. What is it exactly > you would like to know about this ? > !PCIE_LINK_IS_GEN2 means check is for non-Gen2 mode, isn't it? I guess the check should be 'if (PCIE_LINK_IS_GEN2...) > > > >> + /* Enable retrain for gen2 */ > >> + rockchip_pcie_ep_retrain_link(rockchip); > >> + readl_poll_timeout(rockchip->apb_base + PCIE_CORE_CTRL, > >> + val, PCIE_LINK_IS_GEN2(val), 50, > >> + LINK_TRAIN_TIMEOUT); > >> + } > >> + > >> + /* Check again that the link is up */ > >> + if (!rockchip_pcie_ep_link_up(rockchip)) > >> + goto again; > > > > TRM doesn't mention this check. Is this really necessary? > > I think so, to check the result of the second training for gen2. > Even though the TRM does not say so, I prefer checking that the result is what > we expect: the link is up. > Ok. - Mani -- மணிவண்ணன் சதாசிவம்