From: Angelo Dureghello <adureghello@baylibre.com>
To: "Nuno Sá" <nuno.sa@analog.com>,
"Lars-Peter Clausen" <lars@metafoo.de>,
"Michael Hennerich" <Michael.Hennerich@analog.com>,
"Jonathan Cameron" <jic23@kernel.org>,
"Rob Herring" <robh@kernel.org>,
"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
"Conor Dooley" <conor+dt@kernel.org>,
"Olivier Moysan" <olivier.moysan@foss.st.com>
Cc: linux-iio@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, dlechner@baylibre.com,
Mark Brown <broonie@kernel.org>,
Angelo Dureghello <adureghello@baylibre.com>
Subject: [PATCH v6 2/8] dt-bindings: iio: dac: adi-axi-dac: add ad3552r axi variant
Date: Mon, 14 Oct 2024 12:08:08 +0200 [thread overview]
Message-ID: <20241014-wip-bl-ad3552r-axi-v0-iio-testing-v6-2-eeef0c1e0e56@baylibre.com> (raw)
In-Reply-To: <20241014-wip-bl-ad3552r-axi-v0-iio-testing-v6-0-eeef0c1e0e56@baylibre.com>
From: Angelo Dureghello <adureghello@baylibre.com>
Add a new compatible and related bindigns for the fpga-based
"ad3552r" AXI IP core, a variant of the generic AXI DAC IP.
The AXI "ad3552r" IP is a very similar HDL (fpga) variant of the
generic AXI "DAC" IP, intended to control ad3552r and similar chips,
mainly to reach high speed transfer rates using a QSPI DDR
(dobule-data-rate) interface.
The ad3552r device is defined as a child of the AXI DAC, that in
this case is acting as an SPI controller.
Note, #io-backend is present because it is possible (in theory anyway)
to use a separate controller for the control path than that used
for the datapath.
Signed-off-by: Angelo Dureghello <adureghello@baylibre.com>
---
.../devicetree/bindings/iio/dac/adi,axi-dac.yaml | 56 ++++++++++++++++++++--
1 file changed, 53 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/iio/dac/adi,axi-dac.yaml b/Documentation/devicetree/bindings/iio/dac/adi,axi-dac.yaml
index a55e9bfc66d7..2b7e16717219 100644
--- a/Documentation/devicetree/bindings/iio/dac/adi,axi-dac.yaml
+++ b/Documentation/devicetree/bindings/iio/dac/adi,axi-dac.yaml
@@ -19,11 +19,13 @@ description: |
memory via DMA into the DAC.
https://wiki.analog.com/resources/fpga/docs/axi_dac_ip
+ https://analogdevicesinc.github.io/hdl/library/axi_ad3552r/index.html
properties:
compatible:
enum:
- adi,axi-dac-9.1.b
+ - adi,axi-ad3552r
reg:
maxItems: 1
@@ -36,7 +38,14 @@ properties:
- const: tx
clocks:
- maxItems: 1
+ minItems: 1
+ maxItems: 2
+
+ clock-names:
+ minItems: 1
+ items:
+ - const: s_axi_aclk
+ - const: dac_clk
'#io-backend-cells':
const: 0
@@ -47,7 +56,16 @@ required:
- reg
- clocks
-additionalProperties: false
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: adi,axi-ad3552r
+ then:
+ $ref: /schemas/spi/spi-controller.yaml#
+
+unevaluatedProperties: false
examples:
- |
@@ -57,6 +75,38 @@ examples:
dmas = <&tx_dma 0>;
dma-names = "tx";
#io-backend-cells = <0>;
- clocks = <&axi_clk>;
+ clocks = <&clkc 15>;
+ clock-names = "s_axi_aclk";
+ };
+
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+ axi_dac: spi@44a70000 {
+ compatible = "adi,axi-ad3552r";
+ reg = <0x44a70000 0x1000>;
+ dmas = <&dac_tx_dma 0>;
+ dma-names = "tx";
+ #io-backend-cells = <0>;
+ clocks = <&clkc 15>, <&ref_clk>;
+ clock-names = "s_axi_aclk", "dac_clk";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ dac@0 {
+ compatible = "adi,ad3552r";
+ reg = <0>;
+ reset-gpios = <&gpio0 92 GPIO_ACTIVE_HIGH>;
+ io-backends = <&axi_dac>;
+ spi-max-frequency = <66000000>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ channel@0 {
+ reg = <0>;
+ adi,output-range-microvolt = <(-10000000) (10000000)>;
+ };
+ };
};
...
--
2.45.0.rc1
next prev parent reply other threads:[~2024-10-14 10:09 UTC|newest]
Thread overview: 45+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-10-14 10:08 [PATCH v6 0/8] iio: add support for the ad3552r AXI DAC IP Angelo Dureghello
2024-10-14 10:08 ` [PATCH v6 1/8] dt-bindings: iio: dac: ad3552r: add iio backend support Angelo Dureghello
2024-10-14 10:08 ` Angelo Dureghello [this message]
2024-10-14 11:21 ` [PATCH v6 2/8] dt-bindings: iio: dac: adi-axi-dac: add ad3552r axi variant Rob Herring (Arm)
2024-10-14 13:38 ` Rob Herring
2024-10-14 14:04 ` Angelo Dureghello
2024-10-14 19:20 ` Jonathan Cameron
2024-10-14 19:24 ` Angelo Dureghello
2024-10-14 21:13 ` David Lechner
2024-10-15 7:44 ` Angelo Dureghello
2024-10-15 14:40 ` David Lechner
2024-10-15 14:51 ` Nuno Sá
2024-10-15 18:19 ` Angelo Dureghello
2024-10-14 10:08 ` [PATCH v6 3/8] iio: backend: extend features Angelo Dureghello
2024-10-14 10:08 ` [PATCH v6 4/8] iio: dac: adi-axi-dac: " Angelo Dureghello
2024-10-14 21:14 ` David Lechner
2024-10-15 6:30 ` Nuno Sá
2024-10-15 8:57 ` Angelo Dureghello
2024-10-15 11:10 ` Nuno Sá
2024-10-19 15:08 ` Jonathan Cameron
2024-10-14 10:08 ` [PATCH v6 5/8] iio: dac: ad3552r: changes to use FIELD_PREP Angelo Dureghello
2024-10-14 21:14 ` David Lechner
2024-10-15 6:17 ` Nuno Sá
2024-10-15 10:19 ` Angelo Dureghello
2024-10-14 10:08 ` [PATCH v6 6/8] iio: dac: ad3552r: extract common code (no changes in behavior intended) Angelo Dureghello
2024-10-19 15:15 ` Jonathan Cameron
2024-10-14 10:08 ` [PATCH v6 7/8] iio: dac: ad3552r: add high-speed platform driver Angelo Dureghello
2024-10-14 21:15 ` David Lechner
2024-10-15 6:37 ` Nuno Sá
2024-10-15 14:38 ` David Lechner
2024-10-15 15:00 ` Nuno Sá
2024-10-15 15:23 ` David Lechner
2024-10-16 7:50 ` Nuno Sá
2024-10-19 15:18 ` Jonathan Cameron
2024-10-16 8:35 ` Angelo Dureghello
2024-10-15 7:15 ` Nuno Sá
2024-10-15 14:48 ` David Lechner
2024-10-16 11:54 ` Nuno Sá
2024-10-17 7:27 ` Angelo Dureghello
2024-10-19 15:24 ` Jonathan Cameron
2024-10-14 10:08 ` [PATCH v6 8/8] iio: dac: adi-axi-dac: add registering of child fdt node Angelo Dureghello
2024-10-14 21:16 ` David Lechner
2024-10-15 6:11 ` Nuno Sá
2024-10-17 8:32 ` Angelo Dureghello
2024-10-17 15:13 ` Nuno Sá
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