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From: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
To: Krzysztof Kozlowski <krzk@kernel.org>
Cc: Qiang Yu <quic_qianyu@quicinc.com>,
	vkoul@kernel.org, kishon@kernel.org, robh@kernel.org,
	andersson@kernel.org, konradybcio@kernel.org, krzk+dt@kernel.org,
	conor+dt@kernel.org, mturquette@baylibre.com, sboyd@kernel.org,
	abel.vesa@linaro.org, quic_msarkar@quicinc.com,
	quic_devipriy@quicinc.com, dmitry.baryshkov@linaro.org,
	kw@linux.com, lpieralisi@kernel.org, neil.armstrong@linaro.org,
	linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org,
	linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org,
	devicetree@vger.kernel.org, linux-clk@vger.kernel.org
Subject: Re: [PATCH v6 3/8] dt-bindings: PCI: qcom,pcie-x1e80100: Add 'global' interrupt
Date: Mon, 14 Oct 2024 14:32:51 +0530	[thread overview]
Message-ID: <20241014090251.r4sfaaxtasokv4oi@thinkpad> (raw)
In-Reply-To: <df6379c6-662a-4b35-a919-13c695a869c7@kernel.org>

On Fri, Oct 11, 2024 at 06:06:02PM +0200, Krzysztof Kozlowski wrote:
> On 11/10/2024 17:51, Manivannan Sadhasivam wrote:
> > 
> > 
> > On October 11, 2024 9:14:31 PM GMT+05:30, Krzysztof Kozlowski <krzk@kernel.org> wrote:
> >> On 11/10/2024 17:42, Manivannan Sadhasivam wrote:
> >>>
> >>>
> >>> On October 11, 2024 8:03:58 PM GMT+05:30, Krzysztof Kozlowski <krzk@kernel.org> wrote:
> >>>> On Fri, Oct 11, 2024 at 03:41:37AM -0700, Qiang Yu wrote:
> >>>>> Document 'global' SPI interrupt along with the existing MSI interrupts so
> >>>>> that QCOM PCIe RC driver can make use of it to get events such as PCIe
> >>>>> link specific events, safety events, etc.
> >>>>
> >>>> Describe the hardware, not what the driver will do.
> >>>>
> >>>>>
> >>>>> Though adding a new interrupt will break the ABI, it is required to
> >>>>> accurately describe the hardware.
> >>>>
> >>>> That's poor reason. Hardware was described and missing optional piece
> >>>> (because according to your description above everything was working
> >>>> fine) is not needed to break ABI.
> >>>>
> >>>
> >>> Hardware was described but not completely. 'global' IRQ let's the controller driver to handle PCIe link specific events like Link up, Link down etc... They improve user experience like the driver can use those interrupts to start bus enumeration on its own. So breaking the ABI for good in this case.
> >>>
> >>>> Sorry, if your driver changes the ABI for this poor reason.
> >>>>
> >>>
> >>> Is the above reasoning sufficient? 
> >>
> >> I tried to look for corresponding driver change, but could not, so maybe
> >> there is no ABI break in the first place.
> > 
> > Here it is:
> > 
> > https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=4581403f67929d02c197cb187c4e1e811c9e762a
> > 
> >  Above explanation is good, but
> >> still feels like improvement and device could work without global clock.
> 
> So there is no ABI break in the first place... Commit is misleading.
> 

It increases the 'minItems' to 9 from 8, how come it is not an ABI break?

- Mani

-- 
மணிவண்ணன் சதாசிவம்

  parent reply	other threads:[~2024-10-14  9:03 UTC|newest]

Thread overview: 31+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-10-11 10:41 [PATCH v6 0/8] Add support for PCIe3 on x1e80100 Qiang Yu
2024-10-11 10:41 ` [PATCH v6 1/8] dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Document the X1E80100 QMP PCIe PHY Gen4 x8 Qiang Yu
2024-10-12  4:14   ` Manivannan Sadhasivam
2024-10-11 10:41 ` [PATCH v6 2/8] dt-bindings: PCI: qcom: Move OPP table to qcom,pcie-common.yaml Qiang Yu
2024-10-11 10:41 ` [PATCH v6 3/8] dt-bindings: PCI: qcom,pcie-x1e80100: Add 'global' interrupt Qiang Yu
2024-10-11 14:33   ` Krzysztof Kozlowski
2024-10-11 14:36     ` Krzysztof Kozlowski
2024-10-11 15:42     ` Manivannan Sadhasivam
2024-10-11 15:44       ` Krzysztof Kozlowski
2024-10-11 15:51         ` Manivannan Sadhasivam
2024-10-11 16:06           ` Krzysztof Kozlowski
2024-10-14  7:50             ` Qiang Yu
2024-10-14  8:25               ` Krzysztof Kozlowski
2024-10-14 13:09                 ` Qiang Yu
2024-10-14  9:02             ` Manivannan Sadhasivam [this message]
2024-10-14  9:26               ` Krzysztof Kozlowski
2024-10-14  9:41                 ` Manivannan Sadhasivam
2024-10-14 13:09                   ` Qiang Yu
2024-10-11 10:41 ` [PATCH v6 4/8] phy: qcom: qmp: Add phy register and clk setting for x1e80100 PCIe3 Qiang Yu
2024-10-11 10:41 ` [PATCH v6 5/8] clk: qcom: gcc-x1e80100: Fix halt_check for pipediv2 clocks Qiang Yu
2024-10-11 10:41 ` [PATCH v6 6/8] PCI: qcom: Fix the ops for SC8280X family SoC Qiang Yu
2024-10-11 13:36   ` Dmitry Baryshkov
2024-10-12  4:23   ` Manivannan Sadhasivam
2024-10-14 17:18   ` Bjorn Helgaas
2024-10-15  2:46     ` Qiang Yu
2024-10-11 10:41 ` [PATCH v6 7/8] PCI: qcom: Fix the cfg for X1E80100 SoC Qiang Yu
2024-10-11 13:37   ` Dmitry Baryshkov
2024-10-12  5:36   ` Manivannan Sadhasivam
2024-10-14 17:20   ` Bjorn Helgaas
2024-10-11 10:41 ` [PATCH v6 8/8] arm64: dts: qcom: x1e80100: Add support for PCIe3 on x1e80100 Qiang Yu
2024-10-16 20:42 ` (subset) [PATCH v6 0/8] " Bjorn Andersson

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