From: Stanimir Varbanov <svarbanov@suse.de>
To: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-rpi-kernel@lists.infradead.org, linux-pci@vger.kernel.org,
Broadcom internal kernel review list
<bcm-kernel-feedback-list@broadcom.com>
Cc: Thomas Gleixner <tglx@linutronix.de>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Florian Fainelli <florian.fainelli@broadcom.com>,
Jim Quinlan <jim2101024@gmail.com>,
Nicolas Saenz Julienne <nsaenz@kernel.org>,
Bjorn Helgaas <bhelgaas@google.com>,
Lorenzo Pieralisi <lpieralisi@kernel.org>,
kw@linux.com, Philipp Zabel <p.zabel@pengutronix.de>,
Andrea della Porta <andrea.porta@suse.com>,
Phil Elwell <phil@raspberrypi.com>,
Jonathan Bell <jonathan@raspberrypi.com>,
Stanimir Varbanov <svarbanov@suse.de>
Subject: [PATCH v3 10/11] arm64: dts: broadcom: bcm2712: Add PCIe DT nodes
Date: Mon, 14 Oct 2024 16:07:09 +0300 [thread overview]
Message-ID: <20241014130710.413-11-svarbanov@suse.de> (raw)
In-Reply-To: <20241014130710.413-1-svarbanov@suse.de>
Add PCIe devicetree nodes, plus needed reset and mip MSI-X
controllers.
Signed-off-by: Stanimir Varbanov <svarbanov@suse.de>
---
v2 -> v3:
- Added comments on ranges and dma-ranges properties (Florian)
arch/arm64/boot/dts/broadcom/bcm2712.dtsi | 160 ++++++++++++++++++++++
1 file changed, 160 insertions(+)
diff --git a/arch/arm64/boot/dts/broadcom/bcm2712.dtsi b/arch/arm64/boot/dts/broadcom/bcm2712.dtsi
index 6e5a984c1d4e..a83de23856e3 100644
--- a/arch/arm64/boot/dts/broadcom/bcm2712.dtsi
+++ b/arch/arm64/boot/dts/broadcom/bcm2712.dtsi
@@ -192,6 +192,12 @@ soc: soc@107c000000 {
#address-cells = <1>;
#size-cells = <1>;
+ pcie_rescal: reset-controller@119500 {
+ compatible = "brcm,bcm7216-pcie-sata-rescal";
+ reg = <0x00119500 0x10>;
+ #reset-cells = <0>;
+ };
+
sdio1: mmc@fff000 {
compatible = "brcm,bcm2712-sdhci",
"brcm,sdhci-brcmstb";
@@ -204,6 +210,12 @@ sdio1: mmc@fff000 {
mmc-ddr-3_3v;
};
+ bcm_reset: reset-controller@1504318 {
+ compatible = "brcm,brcmstb-reset";
+ reg = <0x01504318 0x30>;
+ #reset-cells = <1>;
+ };
+
system_timer: timer@7c003000 {
compatible = "brcm,bcm2835-system-timer";
reg = <0x7c003000 0x1000>;
@@ -267,6 +279,154 @@ gicv2: interrupt-controller@7fff9000 {
};
};
+ axi@1000000000 {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ ranges = <0x00 0x00000000 0x10 0x00000000 0x01 0x00000000>,
+ <0x14 0x00000000 0x14 0x00000000 0x04 0x00000000>,
+ <0x18 0x00000000 0x18 0x00000000 0x04 0x00000000>,
+ <0x1c 0x00000000 0x1c 0x00000000 0x04 0x00000000>;
+
+ dma-ranges = <0x00 0x00000000 0x00 0x00000000 0x10 0x00000000>,
+ <0x14 0x00000000 0x14 0x00000000 0x04 0x00000000>,
+ <0x18 0x00000000 0x18 0x00000000 0x04 0x00000000>,
+ <0x1c 0x00000000 0x1c 0x00000000 0x04 0x00000000>;
+
+ pcie0: pcie@100000 {
+ compatible = "brcm,bcm2712-pcie";
+ reg = <0x00 0x00100000 0x00 0x9310>;
+ device_type = "pci";
+ linux,pci-domain = <0>;
+ max-link-speed = <2>;
+ bus-range = <0x00 0xff>;
+ num-lanes = <1>;
+ #address-cells = <3>;
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ interrupt-parent = <&gicv2>;
+ interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pcie", "msi";
+ interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+ interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 2 &gicv2 GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 3 &gicv2 GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 4 &gicv2 GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&bcm_reset 42>, <&pcie_rescal>;
+ reset-names = "bridge", "rescal";
+ msi-controller;
+ msi-parent = <&pcie0>;
+
+ ranges =
+ /* ~4GB, 32-bit, non-prefetchable at PCIe 00_0000_0000 */
+ <0x02000000 0x00 0x00000000 0x17 0x00000000 0x00 0xfffffffc>,
+ /* 12GB, 64-bit, prefetchable at PCIe 04_0000_0000 */
+ <0x43000000 0x04 0x00000000 0x14 0x00000000 0x03 0x00000000>;
+
+ dma-ranges =
+ /* 64GB, 64-bit, prefetchable at PCIe 10_0000_0000 */
+ <0x43000000 0x10 0x00000000 0x00 0x00000000 0x10 0x00000000>;
+
+ status = "disabled";
+ };
+
+ pcie1: pcie@110000 {
+ compatible = "brcm,bcm2712-pcie";
+ reg = <0x00 0x00110000 0x00 0x9310>;
+ device_type = "pci";
+ linux,pci-domain = <1>;
+ max-link-speed = <2>;
+ bus-range = <0x00 0xff>;
+ num-lanes = <1>;
+ #address-cells = <3>;
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ interrupt-parent = <&gicv2>;
+ interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pcie", "msi";
+ interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+ interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 2 &gicv2 GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 3 &gicv2 GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 4 &gicv2 GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&bcm_reset 43>, <&pcie_rescal>;
+ reset-names = "bridge", "rescal";
+ msi-parent = <&mip1>;
+
+ ranges =
+ /* ~4GB, 32-bit, non-prefetchable at PCIe 00_0000_0000 */
+ <0x02000000 0x00 0x00000000 0x1b 0x00000000 0x00 0xfffffffc>,
+ /* 12GB, 64-bit, prefetchable at PCIe 04_0000_0000 */
+ <0x43000000 0x04 0x00000000 0x18 0x00000000 0x03 0x00000000>;
+
+ dma-ranges =
+ /* 64GB, 64-bit, non-prefetchable at PCIe 10_0000_0000 */
+ <0x03000000 0x10 0x00000000 0x00 0x00000000 0x10 0x00000000>;
+
+ status = "disabled";
+ };
+
+ pcie2: pcie@120000 {
+ compatible = "brcm,bcm2712-pcie";
+ reg = <0x00 0x00120000 0x00 0x9310>;
+ device_type = "pci";
+ linux,pci-domain = <2>;
+ max-link-speed = <2>;
+ bus-range = <0x00 0xff>;
+ num-lanes = <4>;
+ #address-cells = <3>;
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ interrupt-parent = <&gicv2>;
+ interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pcie", "msi";
+ interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+ interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 2 &gicv2 GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 3 &gicv2 GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 4 &gicv2 GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&bcm_reset 44>, <&pcie_rescal>;
+ reset-names = "bridge", "rescal";
+ msi-parent = <&mip0>;
+
+ ranges =
+ /* ~4GB, 32-bit, non-prefetchable at PCIe 00_0000_0000 */
+ <0x02000000 0x00 0x00000000 0x1f 0x00000000 0x00 0xfffffffc>,
+ /* 12GB, 64-bit, prefetchable at PCIe 04_0000_0000 */
+ <0x43000000 0x04 0x00000000 0x1c 0x00000000 0x03 0x00000000>;
+
+ dma-ranges =
+ /* 4MB, 32-bit, non-prefetchable at PCIe 00_0000_0000 */
+ <0x02000000 0x00 0x00000000 0x1f 0x00000000 0x00 0x00400000>,
+ /* 64GB, 64-bit, prefetchable at PCIe 10_0000_0000 */
+ <0x43000000 0x10 0x00000000 0x00 0x00000000 0x10 0x00000000>;
+
+ status = "disabled";
+ };
+
+ mip0: msi-controller@130000 {
+ compatible = "brcm,bcm2712-mip";
+ reg = <0x00 0x00130000 0x00 0xc0>,
+ <0xff 0xfffff000 0x00 0x1000>;
+ msi-controller;
+ msi-ranges = <&gicv2 GIC_SPI 128 IRQ_TYPE_EDGE_RISING 64>;
+ brcm,msi-offset = <0>;
+ };
+
+ mip1: msi-controller@131000 {
+ compatible = "brcm,bcm2712-mip";
+ reg = <0x00 0x00131000 0x00 0xc0>,
+ <0xff 0xfffff000 0x00 0x1000>;
+ msi-controller;
+ msi-ranges = <&gicv2 GIC_SPI 247 IRQ_TYPE_EDGE_RISING 8>;
+ brcm,msi-offset = <8>;
+ };
+ };
+
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
--
2.43.0
next prev parent reply other threads:[~2024-10-14 13:07 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-10-14 13:06 [PATCH v3 00/11] Add PCIe support for bcm2712 Stanimir Varbanov
2024-10-14 13:07 ` [PATCH v3 01/11] dt-bindings: interrupt-controller: Add bcm2712 MSI-X DT bindings Stanimir Varbanov
2024-10-15 20:11 ` Rob Herring (Arm)
2024-10-14 13:07 ` [PATCH v3 02/11] dt-bindings: PCI: brcmstb: Update bindings for PCIe on bcm2712 Stanimir Varbanov
2024-10-14 13:07 ` [PATCH v3 03/11] irqchip: mip: Add Broadcom bcm2712 MSI-X interrupt controller Stanimir Varbanov
2024-10-14 16:31 ` Thomas Gleixner
2024-10-14 13:07 ` [PATCH v3 04/11] PCI: brcmstb: Expand inbound size calculation helper Stanimir Varbanov
2024-10-14 16:57 ` Bjorn Helgaas
2024-10-14 17:10 ` Florian Fainelli
2024-10-14 17:25 ` Bjorn Helgaas
2024-10-16 17:09 ` Jim Quinlan
2024-10-16 19:38 ` Bjorn Helgaas
2024-10-17 8:02 ` Stanimir Varbanov
2024-10-18 23:31 ` Bjorn Helgaas
2024-10-14 13:07 ` [PATCH v3 05/11] PCI: brcmstb: Enable external MSI-X if available Stanimir Varbanov
2024-10-14 13:07 ` [PATCH v3 06/11] PCI: brcmstb: Avoid turn off of bridge reset Stanimir Varbanov
2024-10-14 17:01 ` Bjorn Helgaas
2024-10-14 17:02 ` Florian Fainelli
2024-10-17 8:07 ` Stanimir Varbanov
2024-10-16 17:17 ` Jim Quinlan
2024-10-17 8:05 ` Stanimir Varbanov
2024-10-14 13:07 ` [PATCH v3 07/11] PCI: brcmstb: Add bcm2712 support Stanimir Varbanov
2024-10-14 13:07 ` [PATCH v3 08/11] PCI: brcmstb: Reuse config structure Stanimir Varbanov
2024-10-14 17:03 ` Bjorn Helgaas
2024-10-17 8:09 ` Stanimir Varbanov
2024-10-14 13:07 ` [PATCH v3 09/11] PCI: brcmstb: Adjust PHY PLL setup to use a 54MHz input refclk Stanimir Varbanov
2024-10-14 17:07 ` Florian Fainelli
2024-10-17 14:42 ` Stanimir Varbanov
2024-10-21 12:56 ` Jonathan Bell
2024-10-21 15:39 ` Stanimir Varbanov
2024-10-14 13:07 ` Stanimir Varbanov [this message]
2024-10-14 13:07 ` [PATCH v3 11/11] arm64: dts: broadcom: bcm2712-rpi-5-b: Enable PCIe DT nodes Stanimir Varbanov
2024-10-14 14:05 ` [PATCH v3 00/11] Add PCIe support for bcm2712 Rob Herring (Arm)
2024-10-14 15:41 ` Stanimir Varbanov
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