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charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20240923-pcie_ep_range-v2-3-78d2ea434d9f@nxp.com> On Mon, Sep 23, 2024 at 02:59:21PM -0400, Frank Li wrote: > Fix hardcoding to Root Complex (RC) mode by adding a drvdata mode check. > Pass PHY_MODE_PCIE_EP if the PCI controller operates in Endpoint (EP) mode. > Patch descriptions should fit within 75 columns. > Fixes: 8026f2d8e8a9 ("PCI: imx6: Call common PHY API to set mode, speed, and submode") > Signed-off-by: Frank Li Reviewed-by: Manivannan Sadhasivam - Mani > --- > drivers/pci/controller/dwc/pci-imx6.c | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) > > diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c > index 808d1f1054173..bdc2b372e6c13 100644 > --- a/drivers/pci/controller/dwc/pci-imx6.c > +++ b/drivers/pci/controller/dwc/pci-imx6.c > @@ -961,7 +961,9 @@ static int imx_pcie_host_init(struct dw_pcie_rp *pp) > goto err_clk_disable; > } > > - ret = phy_set_mode_ext(imx_pcie->phy, PHY_MODE_PCIE, PHY_MODE_PCIE_RC); > + ret = phy_set_mode_ext(imx_pcie->phy, PHY_MODE_PCIE, > + imx_pcie->drvdata->mode == DW_PCIE_EP_TYPE ? > + PHY_MODE_PCIE_EP : PHY_MODE_PCIE_RC); > if (ret) { > dev_err(dev, "unable to set PCIe PHY mode\n"); > goto err_phy_exit; > > -- > 2.34.1 > -- மணிவண்ணன் சதாசிவம்