From: Lothar Rubusch <l.rubusch@gmail.com>
To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org,
dinguyen@kernel.org, marex@denx.de, s.trumtrar@pengutronix.de
Cc: l.rubusch@gmail.com, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: [PATCHv2 00/23] Add Enclustra Arria10 and Cyclone5 SoMs
Date: Sun, 20 Oct 2024 19:40:05 +0000 [thread overview]
Message-ID: <20241020194028.2272371-1-l.rubusch@gmail.com> (raw)
Add device-tree support for the following SoMs:
- Mercury SA1 (cyclone5)
- Mercury+ SA2 (cyclone5)
- Mercury+ AA1 (arria10)
Further add device-tree support for the corresponding carrier boards:
- Mercury+ PE1
- Mercury+ PE3
- Mercury+ ST1
Finally, provide generic support for combinations of the above with
one of the boot-modes
- SD
- eMMC
- QSPI
Almost all of the above can be freely combined. Combinations are
covered by the provided .dts files. This makes an already existing
.dts file obsolete. Further minor fixes of the dtbs_checks are
added separtely.
The current approach shall be partly useful also for corresponding
bootloader integration using dts/upstream. That's also one of the
reasons for the .dtsi split.
Note: Pls, take this as a draft, in particular I have the following
open questions and would appreciate to get some short statement:
1.) Documentation/devicetree/bindings:
Executing the following find...
$ find ./Documentation/devicetree/bindings -name socfpga-\*.txt
...shows 4 text files describing "altr," bindings. I sketch-implemented
the clock binding and could reduce some of my dtbs_check warnings. So, my
questions is, if this is the right way? Shall I try to write .yaml files
for all 4 of them, too? Related to that, who will be maintainer?
2.) Some bindings, e.g. the Silabs clock generator seem to have no
driver, thus show up as warning:
compatible = "silabs,si5338";
IMHO it is most likely rather to be probed/loaded in the SPL of the
bootloader. Is it problematic to keep those declarations (showing up as
warning in dtbs_check) or how to deal with them?
3.) Please, give me some feedback if the DT and binding adjustments are
going into total wrong direction, or where I may do better. If it is ok,
and acceptable, or what is still missing. I tried to split them, to
allow for better single integration / discussion let me know if this is
ok, too.
---
v1 -> v2:
- split bindings and DT adjustments/additions
- add several fixes to the socfpga.dtsi and socfpga_arria10.dtsi where
bindings did not match
- extend existing bindings by properties and nods from arria10 setup
- implement the clock binding altr,socfpga-a10.yaml based on existing
text file, rudimentary datasheet study and requirements of the
particular DT setup
---
Lothar Rubusch (23):
ARM: dts: socfpga: fix typo
ARM: dts: socfpga: align bus name with bindings
ARM: dts: socfpga: align dma name with binding
ARM: dts: socfpga: align fpga-region name
ARM: dts: socfpga: add label to clock manager
ARM: dts: socfpga: add missing cells properties
ARM: dts: socfpga: fix missing ranges
ARM: dts: socfpga: add clock-frequency property
ARM: dts: socfpga: add ranges property to sram
ARM: dts: socfpga: remove arria10 reset-names
ARM: socfpga: dts: add compatibility for arria10
ARM: socfpga: dts: add a10 clock binding yaml
ARM: dts: socfpga: add Enclustra boot-mode dtsi
ARM: dts: socfpga: add Enclustra base-board dtsi
ARM: dts: socfpga: add Enclustra Mercury SA1
dt-bindings: altera: add Enclustra Mercury SA1
ARM: dts: socfpga: add Enclustra Mercury+ SA2
dt-bindings: altera: add binding for Mercury+ SA2
ARM: dts: socfpga: add Mercury AA1 combinations
dt-bindings: altera: add Mercury AA1 combinations
ARM: dts: socfpga: removal of generic PE1 dts
dt-bindings: altera: removal of generic PE1 dts
ARM: dts: socfpga: add Enclustra SoM dts files
.../devicetree/bindings/arm/altera.yaml | 24 ++-
.../bindings/clock/altr,socfpga-a10.yaml | 107 +++++++++++++
.../devicetree/bindings/net/snps,dwmac.yaml | 2 +
arch/arm/boot/dts/intel/socfpga/Makefile | 25 ++-
arch/arm/boot/dts/intel/socfpga/socfpga.dtsi | 6 +-
.../dts/intel/socfpga/socfpga_arria10.dtsi | 26 ++--
.../socfpga/socfpga_arria10_mercury_aa1.dtsi | 141 ++++++++++++++---
.../socfpga_arria10_mercury_aa1_pe1_emmc.dts | 16 ++
.../socfpga_arria10_mercury_aa1_pe1_qspi.dts | 16 ++
.../socfpga_arria10_mercury_aa1_pe1_sdmmc.dts | 16 ++
.../socfpga_arria10_mercury_aa1_pe3_emmc.dts | 16 ++
.../socfpga_arria10_mercury_aa1_pe3_qspi.dts | 16 ++
.../socfpga_arria10_mercury_aa1_pe3_sdmmc.dts | 16 ++
.../socfpga_arria10_mercury_aa1_st1_emmc.dts | 16 ++
.../socfpga_arria10_mercury_aa1_st1_qspi.dts | 16 ++
.../socfpga_arria10_mercury_aa1_st1_sdmmc.dts | 16 ++
.../socfpga/socfpga_arria10_mercury_pe1.dts | 55 -------
.../socfpga/socfpga_cyclone5_mercury_sa1.dtsi | 143 +++++++++++++++++
.../socfpga_cyclone5_mercury_sa1_pe1_emmc.dts | 16 ++
.../socfpga_cyclone5_mercury_sa1_pe1_qspi.dts | 16 ++
...socfpga_cyclone5_mercury_sa1_pe1_sdmmc.dts | 16 ++
.../socfpga_cyclone5_mercury_sa1_pe3_emmc.dts | 16 ++
.../socfpga_cyclone5_mercury_sa1_pe3_qspi.dts | 16 ++
...socfpga_cyclone5_mercury_sa1_pe3_sdmmc.dts | 16 ++
.../socfpga_cyclone5_mercury_sa1_st1_emmc.dts | 16 ++
.../socfpga_cyclone5_mercury_sa1_st1_qspi.dts | 16 ++
...socfpga_cyclone5_mercury_sa1_st1_sdmmc.dts | 16 ++
.../socfpga/socfpga_cyclone5_mercury_sa2.dtsi | 146 ++++++++++++++++++
.../socfpga_cyclone5_mercury_sa2_pe1_qspi.dts | 16 ++
...socfpga_cyclone5_mercury_sa2_pe1_sdmmc.dts | 16 ++
.../socfpga_cyclone5_mercury_sa2_pe3_qspi.dts | 16 ++
...socfpga_cyclone5_mercury_sa2_pe3_sdmmc.dts | 16 ++
.../socfpga_cyclone5_mercury_sa2_st1_qspi.dts | 16 ++
...socfpga_cyclone5_mercury_sa2_st1_sdmmc.dts | 16 ++
...cfpga_enclustra_mercury_bootmode_emmc.dtsi | 12 ++
...cfpga_enclustra_mercury_bootmode_qspi.dtsi | 8 +
...fpga_enclustra_mercury_bootmode_sdmmc.dtsi | 8 +
.../socfpga_enclustra_mercury_pe1.dtsi | 33 ++++
.../socfpga_enclustra_mercury_pe3.dtsi | 55 +++++++
.../socfpga_enclustra_mercury_st1.dtsi | 15 ++
40 files changed, 1097 insertions(+), 93 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/altr,socfpga-a10.yaml
create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe1_emmc.dts
create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe1_qspi.dts
create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe1_sdmmc.dts
create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe3_emmc.dts
create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe3_qspi.dts
create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_pe3_sdmmc.dts
create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_st1_emmc.dts
create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_st1_qspi.dts
create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_aa1_st1_sdmmc.dts
delete mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_arria10_mercury_pe1.dts
create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1.dtsi
create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe1_emmc.dts
create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe1_qspi.dts
create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe1_sdmmc.dts
create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe3_emmc.dts
create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe3_qspi.dts
create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe3_sdmmc.dts
create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_st1_emmc.dts
create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_st1_qspi.dts
create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_st1_sdmmc.dts
create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2.dtsi
create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_pe1_qspi.dts
create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_pe1_sdmmc.dts
create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_pe3_qspi.dts
create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_pe3_sdmmc.dts
create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_st1_qspi.dts
create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_st1_sdmmc.dts
create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_bootmode_emmc.dtsi
create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_bootmode_qspi.dtsi
create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_bootmode_sdmmc.dtsi
create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_pe1.dtsi
create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_pe3.dtsi
create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_st1.dtsi
--
2.25.1
next reply other threads:[~2024-10-20 19:40 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-10-20 19:40 Lothar Rubusch [this message]
2024-10-20 19:40 ` [PATCHv2 01/23] ARM: dts: socfpga: fix typo Lothar Rubusch
2024-10-20 19:40 ` [PATCHv2 02/23] ARM: dts: socfpga: align bus name with bindings Lothar Rubusch
2024-10-20 19:40 ` [PATCHv2 03/23] ARM: dts: socfpga: align dma name with binding Lothar Rubusch
2024-10-20 19:40 ` [PATCHv2 04/23] ARM: dts: socfpga: align fpga-region name Lothar Rubusch
2024-10-20 19:40 ` [PATCHv2 05/23] ARM: dts: socfpga: add label to clock manager Lothar Rubusch
2024-10-20 19:40 ` [PATCHv2 06/23] ARM: dts: socfpga: add missing cells properties Lothar Rubusch
2024-10-20 19:40 ` [PATCHv2 07/23] ARM: dts: socfpga: fix missing ranges Lothar Rubusch
2024-10-20 19:40 ` [PATCHv2 08/23] ARM: dts: socfpga: add clock-frequency property Lothar Rubusch
2024-10-20 19:40 ` [PATCHv2 09/23] ARM: dts: socfpga: add ranges property to sram Lothar Rubusch
2024-10-20 19:40 ` [PATCHv2 10/23] ARM: dts: socfpga: remove arria10 reset-names Lothar Rubusch
2024-10-20 19:40 ` [PATCHv2 11/23] ARM: socfpga: dts: add compatibility for arria10 Lothar Rubusch
2024-10-21 7:05 ` Krzysztof Kozlowski
2024-10-20 19:40 ` [PATCHv2 12/23] ARM: socfpga: dts: add a10 clock binding yaml Lothar Rubusch
2024-10-20 22:21 ` Rob Herring (Arm)
2024-10-21 7:04 ` Krzysztof Kozlowski
2024-10-24 6:10 ` Lothar Rubusch
2024-10-24 6:24 ` Krzysztof Kozlowski
2024-10-25 6:59 ` Lothar Rubusch
2024-10-25 8:01 ` Krzysztof Kozlowski
2024-10-20 19:40 ` [PATCHv2 13/23] ARM: dts: socfpga: add Enclustra boot-mode dtsi Lothar Rubusch
2024-10-23 17:20 ` Ahmad Fatoum
2024-10-24 6:15 ` Lothar Rubusch
2024-10-20 19:40 ` [PATCHv2 14/23] ARM: dts: socfpga: add Enclustra base-board dtsi Lothar Rubusch
2024-10-20 19:40 ` [PATCHv2 15/23] ARM: dts: socfpga: add Enclustra Mercury SA1 Lothar Rubusch
2024-10-20 19:40 ` [PATCHv2 16/23] dt-bindings: altera: " Lothar Rubusch
2024-10-21 7:47 ` Krzysztof Kozlowski
2024-10-20 19:40 ` [PATCHv2 17/23] ARM: dts: socfpga: add Enclustra Mercury+ SA2 Lothar Rubusch
2024-10-20 19:40 ` [PATCHv2 18/23] dt-bindings: altera: add binding for " Lothar Rubusch
2024-10-21 7:47 ` Krzysztof Kozlowski
2024-10-20 19:40 ` [PATCHv2 19/23] ARM: dts: socfpga: add Mercury AA1 combinations Lothar Rubusch
2024-10-20 19:40 ` [PATCHv2 20/23] dt-bindings: altera: " Lothar Rubusch
2024-10-21 7:48 ` Krzysztof Kozlowski
2024-10-20 19:40 ` [PATCHv2 21/23] ARM: dts: socfpga: removal of generic PE1 dts Lothar Rubusch
2024-10-20 19:40 ` [PATCHv2 22/23] dt-bindings: altera: " Lothar Rubusch
2024-10-21 7:48 ` Krzysztof Kozlowski
2024-10-20 19:40 ` [PATCHv2 23/23] ARM: dts: socfpga: add Enclustra SoM dts files Lothar Rubusch
2024-10-21 17:58 ` [PATCHv2 00/23] Add Enclustra Arria10 and Cyclone5 SoMs Rob Herring (Arm)
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