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From: Lothar Rubusch <l.rubusch@gmail.com>
To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org,
	dinguyen@kernel.org, marex@denx.de, s.trumtrar@pengutronix.de
Cc: l.rubusch@gmail.com, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org
Subject: [PATCHv2 14/23] ARM: dts: socfpga: add Enclustra base-board dtsi
Date: Sun, 20 Oct 2024 19:40:19 +0000	[thread overview]
Message-ID: <20241020194028.2272371-15-l.rubusch@gmail.com> (raw)
In-Reply-To: <20241020194028.2272371-1-l.rubusch@gmail.com>

Add generic Enclustra base-board support for the Mercury+ PE1, the
Mercury+ PE3 and the Mercury+ ST1 board. The carrier boards can be
freely combined with the SoMs Mercury+ AA1, Mercury SA1 and
Mercury+ SA2.

Signed-off-by: Andreas Buerkler <andreas.buerkler@enclustra.com>
Signed-off-by: Lothar Rubusch <l.rubusch@gmail.com>
---
 .../socfpga_enclustra_mercury_pe1.dtsi        | 33 +++++++++++
 .../socfpga_enclustra_mercury_pe3.dtsi        | 55 +++++++++++++++++++
 .../socfpga_enclustra_mercury_st1.dtsi        | 15 +++++
 3 files changed, 103 insertions(+)
 create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_pe1.dtsi
 create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_pe3.dtsi
 create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_st1.dtsi

diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_pe1.dtsi b/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_pe1.dtsi
new file mode 100644
index 000000000..11f418e88
--- /dev/null
+++ b/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_pe1.dtsi
@@ -0,0 +1,33 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com
+ */
+
+&i2c_encl {
+	status = "okay";
+
+	24aa128@57 {
+		status = "okay";
+		compatible = "microchip,24c128";
+		reg = <0x57>;
+		pagesize = <64>;
+		label = "user eeprom";
+		address-width = <16>;
+	};
+
+	lm96080@2f {
+		status = "okay";
+		compatible = "national,lm80";
+		reg = <0x2f>;
+	};
+
+	si5338@70 {
+		compatible = "silabs,si5338";
+		reg = <0x70>;
+	};
+
+};
+
+&i2c_encl_fpga {
+	status = "okay";
+};
diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_pe3.dtsi b/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_pe3.dtsi
new file mode 100644
index 000000000..9fbde91ad
--- /dev/null
+++ b/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_pe3.dtsi
@@ -0,0 +1,55 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com
+ */
+
+&i2c_encl {
+	i2c-mux@74 {
+		status = "okay";
+		compatible = "nxp,pca9547";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x74>;
+
+		i2c@0 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0>;
+
+			24aa128@56 {
+				status = "okay";
+				compatible = "microchip,24c128";
+				reg = <0x56>;
+				pagesize = <64>;
+				label = "user eeprom";
+				address-width = <16>;
+			};
+
+			lm96080@2f {
+				status = "okay";
+				compatible = "national,lm80";
+				reg = <0x2f>;
+			};
+
+			pcal6416@20 {
+				status = "okay";
+				compatible = "nxp,pcal6416";
+				reg = <0x20>;
+				gpio-controller;
+				#gpio-cells = <2>;
+			};
+		};
+	};
+};
+
+&i2c_encl_fpga {
+	status = "okay";
+
+	i2c-mux@75 {
+		status = "okay";
+		compatible = "nxp,pca9547";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x75>;
+	};
+};
diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_st1.dtsi b/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_st1.dtsi
new file mode 100644
index 000000000..ffcef353e
--- /dev/null
+++ b/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_st1.dtsi
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com
+ */
+
+&i2c_encl {
+	si5338@70 {
+		compatible = "silabs,si5338";
+		reg = <0x70>;
+	};
+};
+
+&i2c_encl_fpga {
+	status = "okay";
+};
-- 
2.25.1


  parent reply	other threads:[~2024-10-20 19:40 UTC|newest]

Thread overview: 38+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-10-20 19:40 [PATCHv2 00/23] Add Enclustra Arria10 and Cyclone5 SoMs Lothar Rubusch
2024-10-20 19:40 ` [PATCHv2 01/23] ARM: dts: socfpga: fix typo Lothar Rubusch
2024-10-20 19:40 ` [PATCHv2 02/23] ARM: dts: socfpga: align bus name with bindings Lothar Rubusch
2024-10-20 19:40 ` [PATCHv2 03/23] ARM: dts: socfpga: align dma name with binding Lothar Rubusch
2024-10-20 19:40 ` [PATCHv2 04/23] ARM: dts: socfpga: align fpga-region name Lothar Rubusch
2024-10-20 19:40 ` [PATCHv2 05/23] ARM: dts: socfpga: add label to clock manager Lothar Rubusch
2024-10-20 19:40 ` [PATCHv2 06/23] ARM: dts: socfpga: add missing cells properties Lothar Rubusch
2024-10-20 19:40 ` [PATCHv2 07/23] ARM: dts: socfpga: fix missing ranges Lothar Rubusch
2024-10-20 19:40 ` [PATCHv2 08/23] ARM: dts: socfpga: add clock-frequency property Lothar Rubusch
2024-10-20 19:40 ` [PATCHv2 09/23] ARM: dts: socfpga: add ranges property to sram Lothar Rubusch
2024-10-20 19:40 ` [PATCHv2 10/23] ARM: dts: socfpga: remove arria10 reset-names Lothar Rubusch
2024-10-20 19:40 ` [PATCHv2 11/23] ARM: socfpga: dts: add compatibility for arria10 Lothar Rubusch
2024-10-21  7:05   ` Krzysztof Kozlowski
2024-10-20 19:40 ` [PATCHv2 12/23] ARM: socfpga: dts: add a10 clock binding yaml Lothar Rubusch
2024-10-20 22:21   ` Rob Herring (Arm)
2024-10-21  7:04   ` Krzysztof Kozlowski
2024-10-24  6:10     ` Lothar Rubusch
2024-10-24  6:24       ` Krzysztof Kozlowski
2024-10-25  6:59         ` Lothar Rubusch
2024-10-25  8:01           ` Krzysztof Kozlowski
2024-10-20 19:40 ` [PATCHv2 13/23] ARM: dts: socfpga: add Enclustra boot-mode dtsi Lothar Rubusch
2024-10-23 17:20   ` Ahmad Fatoum
2024-10-24  6:15     ` Lothar Rubusch
2024-10-20 19:40 ` Lothar Rubusch [this message]
2024-10-20 19:40 ` [PATCHv2 15/23] ARM: dts: socfpga: add Enclustra Mercury SA1 Lothar Rubusch
2024-10-20 19:40 ` [PATCHv2 16/23] dt-bindings: altera: " Lothar Rubusch
2024-10-21  7:47   ` Krzysztof Kozlowski
2024-10-20 19:40 ` [PATCHv2 17/23] ARM: dts: socfpga: add Enclustra Mercury+ SA2 Lothar Rubusch
2024-10-20 19:40 ` [PATCHv2 18/23] dt-bindings: altera: add binding for " Lothar Rubusch
2024-10-21  7:47   ` Krzysztof Kozlowski
2024-10-20 19:40 ` [PATCHv2 19/23] ARM: dts: socfpga: add Mercury AA1 combinations Lothar Rubusch
2024-10-20 19:40 ` [PATCHv2 20/23] dt-bindings: altera: " Lothar Rubusch
2024-10-21  7:48   ` Krzysztof Kozlowski
2024-10-20 19:40 ` [PATCHv2 21/23] ARM: dts: socfpga: removal of generic PE1 dts Lothar Rubusch
2024-10-20 19:40 ` [PATCHv2 22/23] dt-bindings: altera: " Lothar Rubusch
2024-10-21  7:48   ` Krzysztof Kozlowski
2024-10-20 19:40 ` [PATCHv2 23/23] ARM: dts: socfpga: add Enclustra SoM dts files Lothar Rubusch
2024-10-21 17:58 ` [PATCHv2 00/23] Add Enclustra Arria10 and Cyclone5 SoMs Rob Herring (Arm)

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