From: Lothar Rubusch <l.rubusch@gmail.com>
To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org,
dinguyen@kernel.org, marex@denx.de, s.trumtrar@pengutronix.de
Cc: l.rubusch@gmail.com, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: [PATCHv2 01/23] ARM: dts: socfpga: fix typo
Date: Sun, 20 Oct 2024 19:40:06 +0000 [thread overview]
Message-ID: <20241020194028.2272371-2-l.rubusch@gmail.com> (raw)
In-Reply-To: <20241020194028.2272371-1-l.rubusch@gmail.com>
A semicolon was fallen off the wall.
Signed-off-by: Lothar Rubusch <l.rubusch@gmail.com>
---
arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi
index 6b6e77596..7113fe5b5 100644
--- a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi
+++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi
@@ -169,8 +169,7 @@ main_gpio_db_clk: main_gpio_db_clk@74 {
main_sdmmc_clk: main_sdmmc_clk@78 {
#clock-cells = <0>;
- compatible = "altr,socfpga-a10-perip-clk"
-;
+ compatible = "altr,socfpga-a10-perip-clk";
clocks = <&main_pll>;
reg = <0x78>;
};
--
2.25.1
next prev parent reply other threads:[~2024-10-20 19:40 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-10-20 19:40 [PATCHv2 00/23] Add Enclustra Arria10 and Cyclone5 SoMs Lothar Rubusch
2024-10-20 19:40 ` Lothar Rubusch [this message]
2024-10-20 19:40 ` [PATCHv2 02/23] ARM: dts: socfpga: align bus name with bindings Lothar Rubusch
2024-10-20 19:40 ` [PATCHv2 03/23] ARM: dts: socfpga: align dma name with binding Lothar Rubusch
2024-10-20 19:40 ` [PATCHv2 04/23] ARM: dts: socfpga: align fpga-region name Lothar Rubusch
2024-10-20 19:40 ` [PATCHv2 05/23] ARM: dts: socfpga: add label to clock manager Lothar Rubusch
2024-10-20 19:40 ` [PATCHv2 06/23] ARM: dts: socfpga: add missing cells properties Lothar Rubusch
2024-10-20 19:40 ` [PATCHv2 07/23] ARM: dts: socfpga: fix missing ranges Lothar Rubusch
2024-10-20 19:40 ` [PATCHv2 08/23] ARM: dts: socfpga: add clock-frequency property Lothar Rubusch
2024-10-20 19:40 ` [PATCHv2 09/23] ARM: dts: socfpga: add ranges property to sram Lothar Rubusch
2024-10-20 19:40 ` [PATCHv2 10/23] ARM: dts: socfpga: remove arria10 reset-names Lothar Rubusch
2024-10-20 19:40 ` [PATCHv2 11/23] ARM: socfpga: dts: add compatibility for arria10 Lothar Rubusch
2024-10-21 7:05 ` Krzysztof Kozlowski
2024-10-20 19:40 ` [PATCHv2 12/23] ARM: socfpga: dts: add a10 clock binding yaml Lothar Rubusch
2024-10-20 22:21 ` Rob Herring (Arm)
2024-10-21 7:04 ` Krzysztof Kozlowski
2024-10-24 6:10 ` Lothar Rubusch
2024-10-24 6:24 ` Krzysztof Kozlowski
2024-10-25 6:59 ` Lothar Rubusch
2024-10-25 8:01 ` Krzysztof Kozlowski
2024-10-20 19:40 ` [PATCHv2 13/23] ARM: dts: socfpga: add Enclustra boot-mode dtsi Lothar Rubusch
2024-10-23 17:20 ` Ahmad Fatoum
2024-10-24 6:15 ` Lothar Rubusch
2024-10-20 19:40 ` [PATCHv2 14/23] ARM: dts: socfpga: add Enclustra base-board dtsi Lothar Rubusch
2024-10-20 19:40 ` [PATCHv2 15/23] ARM: dts: socfpga: add Enclustra Mercury SA1 Lothar Rubusch
2024-10-20 19:40 ` [PATCHv2 16/23] dt-bindings: altera: " Lothar Rubusch
2024-10-21 7:47 ` Krzysztof Kozlowski
2024-10-20 19:40 ` [PATCHv2 17/23] ARM: dts: socfpga: add Enclustra Mercury+ SA2 Lothar Rubusch
2024-10-20 19:40 ` [PATCHv2 18/23] dt-bindings: altera: add binding for " Lothar Rubusch
2024-10-21 7:47 ` Krzysztof Kozlowski
2024-10-20 19:40 ` [PATCHv2 19/23] ARM: dts: socfpga: add Mercury AA1 combinations Lothar Rubusch
2024-10-20 19:40 ` [PATCHv2 20/23] dt-bindings: altera: " Lothar Rubusch
2024-10-21 7:48 ` Krzysztof Kozlowski
2024-10-20 19:40 ` [PATCHv2 21/23] ARM: dts: socfpga: removal of generic PE1 dts Lothar Rubusch
2024-10-20 19:40 ` [PATCHv2 22/23] dt-bindings: altera: " Lothar Rubusch
2024-10-21 7:48 ` Krzysztof Kozlowski
2024-10-20 19:40 ` [PATCHv2 23/23] ARM: dts: socfpga: add Enclustra SoM dts files Lothar Rubusch
2024-10-21 17:58 ` [PATCHv2 00/23] Add Enclustra Arria10 and Cyclone5 SoMs Rob Herring (Arm)
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