From: Daniel Machon <daniel.machon@microchip.com>
To: "David S. Miller" <davem@davemloft.net>,
Eric Dumazet <edumazet@google.com>,
Jakub Kicinski <kuba@kernel.org>, Paolo Abeni <pabeni@redhat.com>,
<andrew@lunn.ch>, Lars Povlsen <lars.povlsen@microchip.com>,
Steen Hegelund <Steen.Hegelund@microchip.com>,
<horatiu.vultur@microchip.com>,
<jensemil.schulzostergaard@microchip.com>,
<Parthiban.Veerasooran@microchip.com>,
<Raju.Lakkaraju@microchip.com>, <UNGLinuxDriver@microchip.com>,
Richard Cochran <richardcochran@gmail.com>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>, <jacob.e.keller@intel.com>,
<ast@fiberby.net>, <maxime.chevallier@bootlin.com>
Cc: <netdev@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org>,
<linux-kernel@vger.kernel.org>,
Steen Hegelund <steen.hegelund@microchip.com>,
<devicetree@vger.kernel.org>
Subject: [PATCH net-next 05/15] net: sparx5: add registers required by lan969x
Date: Mon, 21 Oct 2024 15:58:42 +0200 [thread overview]
Message-ID: <20241021-sparx5-lan969x-switch-driver-2-v1-5-c8c49ef21e0f@microchip.com> (raw)
In-Reply-To: <20241021-sparx5-lan969x-switch-driver-2-v1-0-c8c49ef21e0f@microchip.com>
Lan969x will require a few additional registers for certain operations.
Some are shared, some are not. Add these.
Reviewed-by: Steen Hegelund <Steen.Hegelund@microchip.com>
Signed-off-by: Daniel Machon <daniel.machon@microchip.com>
---
.../ethernet/microchip/sparx5/sparx5_main_regs.h | 132 +++++++++++++++++++++
1 file changed, 132 insertions(+)
diff --git a/drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h b/drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h
index 0e8b18bcf179..34cfbc719ca5 100644
--- a/drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h
+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h
@@ -2666,6 +2666,44 @@ extern const struct sparx5_regs *regs;
#define CPU_PROC_CTRL_ACP_DISABLE_GET(x)\
FIELD_GET(CPU_PROC_CTRL_ACP_DISABLE, x)
+/* DEV1G:PHASE_DETECTOR_CTRL:PHAD_CTRL */
+#define DEV2G5_PHAD_CTRL(t, g) \
+ __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 200, g, 2, \
+ regs->gsize[GW_DEV2G5_PHASE_DETECTOR_CTRL], 0, 0, 1, 4)
+
+#define DEV2G5_PHAD_CTRL_PHAD_ENA\
+ BIT(regs->fpos[FP_DEV2G5_PHAD_CTRL_PHAD_ENA])
+#define DEV2G5_PHAD_CTRL_PHAD_ENA_SET(x)\
+ spx5_field_prep(DEV2G5_PHAD_CTRL_PHAD_ENA, x)
+#define DEV2G5_PHAD_CTRL_PHAD_ENA_GET(x)\
+ spx5_field_get(DEV2G5_PHAD_CTRL_PHAD_ENA, x)
+
+/* LAN969X ONLY */
+#define DEV2G5_PHAD_CTRL_DIV_CFG GENMASK(11, 9)
+#define DEV2G5_PHAD_CTRL_DIV_CFG_SET(x)\
+ FIELD_PREP(DEV2G5_PHAD_CTRL_DIV_CFG, x)
+#define DEV2G5_PHAD_CTRL_DIV_CFG_GET(x)\
+ FIELD_GET(DEV2G5_PHAD_CTRL_DIV_CFG, x)
+
+/* DEV1G:PHASE_DETECTOR_CTRL:PHAD_CTRL */
+#define DEV2G5_PHAD_CTRL(t, g) \
+ __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 200, g, 2, \
+ regs->gsize[GW_DEV2G5_PHASE_DETECTOR_CTRL], 0, 0, 1, 4)
+
+#define DEV2G5_PHAD_CTRL_PHAD_ENA\
+ BIT(regs->fpos[FP_DEV2G5_PHAD_CTRL_PHAD_ENA])
+#define DEV2G5_PHAD_CTRL_PHAD_ENA_SET(x)\
+ spx5_field_prep(DEV2G5_PHAD_CTRL_PHAD_ENA, x)
+#define DEV2G5_PHAD_CTRL_PHAD_ENA_GET(x)\
+ spx5_field_get(DEV2G5_PHAD_CTRL_PHAD_ENA, x)
+
+/* LAN969X ONLY */
+#define DEV2G5_PHAD_CTRL_DIV_CFG GENMASK(11, 9)
+#define DEV2G5_PHAD_CTRL_DIV_CFG_SET(x)\
+ FIELD_PREP(DEV2G5_PHAD_CTRL_DIV_CFG, x)
+#define DEV2G5_PHAD_CTRL_DIV_CFG_GET(x)\
+ FIELD_GET(DEV2G5_PHAD_CTRL_DIV_CFG, x)
+
/* DEV10G:MAC_CFG_STATUS:MAC_ENA_CFG */
#define DEV10G_MAC_ENA_CFG(t) \
__REG(TARGET_DEV10G, t, regs->tsize[TC_DEV10G], 0, 0, 1, 60, 0, 0, 1, \
@@ -2869,6 +2907,11 @@ extern const struct sparx5_regs *regs;
#define DEV10G_DEV_RST_CTRL_MAC_RX_RST_GET(x)\
FIELD_GET(DEV10G_DEV_RST_CTRL_MAC_RX_RST, x)
+/* DEV10G:DEV_CFG_STATUS:PTP_STAMPER_CFG */
+#define DEV10G_PTP_STAMPER_CFG(t) \
+ __REG(TARGET_DEV10G, t, regs->tsize[TC_DEV10G], 436, 0, 1, 52, 20, 0, \
+ 1, 4)
+
/* DEV10G:PCS25G_CFG_STATUS:PCS25G_CFG */
#define DEV10G_PCS25G_CFG(t) \
__REG(TARGET_DEV10G, t, regs->tsize[TC_DEV10G], 488, 0, 1, 32, 0, 0, 1,\
@@ -4267,6 +4310,11 @@ extern const struct sparx5_regs *regs;
#define DEV5G_DEV_RST_CTRL_MAC_RX_RST_GET(x)\
FIELD_GET(DEV5G_DEV_RST_CTRL_MAC_RX_RST, x)
+/* DEV10G:DEV_CFG_STATUS:PTP_STAMPER_CFG */
+#define DEV5G_PTP_STAMPER_CFG(t) \
+ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 436, 0, 1, 52, 20, 0, 1, \
+ 4)
+
/* DSM:RAM_CTRL:RAM_INIT */
#define DSM_RAM_INIT \
__REG(TARGET_DSM, 0, 1, 0, 0, 1, 4, 0, 0, 1, 4)
@@ -4444,6 +4492,27 @@ extern const struct sparx5_regs *regs;
#define DSM_TAXI_CAL_CFG_CAL_PGM_ENA_GET(x)\
FIELD_GET(DSM_TAXI_CAL_CFG_CAL_PGM_ENA, x)
+/* LAN969X ONLY */
+#define DSM_TAXI_CAL_CFG_CAL_SEL_STAT BIT(23)
+#define DSM_TAXI_CAL_CFG_CAL_SEL_STAT_SET(x)\
+ FIELD_PREP(DSM_TAXI_CAL_CFG_CAL_SEL_STAT, x)
+#define DSM_TAXI_CAL_CFG_CAL_SEL_STAT_GET(x)\
+ FIELD_GET(DSM_TAXI_CAL_CFG_CAL_SEL_STAT, x)
+
+/* LAN969X ONLY */
+#define DSM_TAXI_CAL_CFG_CAL_SWITCH BIT(22)
+#define DSM_TAXI_CAL_CFG_CAL_SWITCH_SET(x)\
+ FIELD_PREP(DSM_TAXI_CAL_CFG_CAL_SWITCH, x)
+#define DSM_TAXI_CAL_CFG_CAL_SWITCH_GET(x)\
+ FIELD_GET(DSM_TAXI_CAL_CFG_CAL_SWITCH, x)
+
+/* LAN969X ONLY */
+#define DSM_TAXI_CAL_CFG_CAL_PGM_SEL BIT(21)
+#define DSM_TAXI_CAL_CFG_CAL_PGM_SEL_SET(x)\
+ FIELD_PREP(DSM_TAXI_CAL_CFG_CAL_PGM_SEL, x)
+#define DSM_TAXI_CAL_CFG_CAL_PGM_SEL_GET(x)\
+ FIELD_GET(DSM_TAXI_CAL_CFG_CAL_PGM_SEL, x)
+
/* EACL:ES2_KEY_SELECT_PROFILE:VCAP_ES2_KEY_SEL */
#define EACL_VCAP_ES2_KEY_SEL(g, r) \
__REG(TARGET_EACL, 0, 1, regs->gaddr[GA_EACL_ES2_KEY_SELECT_PROFILE], \
@@ -6720,6 +6789,69 @@ extern const struct sparx5_regs *regs;
regs->gcnt[GC_PTP_PHASE_DETECTOR_CTRL], \
regs->gsize[GW_PTP_PHASE_DETECTOR_CTRL], 4, 0, 1, 4)
+/* LAN969X ONLY */
+/* DEVCPU_PTP:PTP_TS_FIFO:PTP_TWOSTEP_CTRL */
+#define PTP_PTP_TWOSTEP_CTRL \
+ __REG(TARGET_PTP, 0, 1, 612, 0, 1, 16, 0, 0, 1, 4)
+
+#define PTP_PTP_TWOSTEP_CTRL_PTP_OVWR_ENA BIT(12)
+#define PTP_PTP_TWOSTEP_CTRL_PTP_OVWR_ENA_SET(x)\
+ FIELD_PREP(PTP_PTP_TWOSTEP_CTRL_PTP_OVWR_ENA, x)
+#define PTP_PTP_TWOSTEP_CTRL_PTP_OVWR_ENA_GET(x)\
+ FIELD_GET(PTP_PTP_TWOSTEP_CTRL_PTP_OVWR_ENA, x)
+
+#define PTP_PTP_TWOSTEP_CTRL_PTP_NXT BIT(11)
+#define PTP_PTP_TWOSTEP_CTRL_PTP_NXT_SET(x)\
+ FIELD_PREP(PTP_PTP_TWOSTEP_CTRL_PTP_NXT, x)
+#define PTP_PTP_TWOSTEP_CTRL_PTP_NXT_GET(x)\
+ FIELD_GET(PTP_PTP_TWOSTEP_CTRL_PTP_NXT, x)
+
+#define PTP_PTP_TWOSTEP_CTRL_PTP_VLD BIT(10)
+#define PTP_PTP_TWOSTEP_CTRL_PTP_VLD_SET(x)\
+ FIELD_PREP(PTP_PTP_TWOSTEP_CTRL_PTP_VLD, x)
+#define PTP_PTP_TWOSTEP_CTRL_PTP_VLD_GET(x)\
+ FIELD_GET(PTP_PTP_TWOSTEP_CTRL_PTP_VLD, x)
+
+#define PTP_PTP_TWOSTEP_CTRL_STAMP_TX BIT(9)
+#define PTP_PTP_TWOSTEP_CTRL_STAMP_TX_SET(x)\
+ FIELD_PREP(PTP_PTP_TWOSTEP_CTRL_STAMP_TX, x)
+#define PTP_PTP_TWOSTEP_CTRL_STAMP_TX_GET(x)\
+ FIELD_GET(PTP_PTP_TWOSTEP_CTRL_STAMP_TX, x)
+
+#define PTP_PTP_TWOSTEP_CTRL_STAMP_PORT GENMASK(8, 1)
+#define PTP_PTP_TWOSTEP_CTRL_STAMP_PORT_SET(x)\
+ FIELD_PREP(PTP_PTP_TWOSTEP_CTRL_STAMP_PORT, x)
+#define PTP_PTP_TWOSTEP_CTRL_STAMP_PORT_GET(x)\
+ FIELD_GET(PTP_PTP_TWOSTEP_CTRL_STAMP_PORT, x)
+
+#define PTP_PTP_TWOSTEP_CTRL_PTP_OVFL BIT(0)
+#define PTP_PTP_TWOSTEP_CTRL_PTP_OVFL_SET(x)\
+ FIELD_PREP(PTP_PTP_TWOSTEP_CTRL_PTP_OVFL, x)
+#define PTP_PTP_TWOSTEP_CTRL_PTP_OVFL_GET(x)\
+ FIELD_GET(PTP_PTP_TWOSTEP_CTRL_PTP_OVFL, x)
+
+/* LAN969X ONLY */
+/* DEVCPU_PTP:PTP_TS_FIFO:PTP_TWOSTEP_STAMP_NSEC */
+#define PTP_PTP_TWOSTEP_STAMP_NSEC \
+ __REG(TARGET_PTP, 0, 1, 612, 0, 1, 16, 4, 0, 1, 4)
+
+#define PTP_PTP_TWOSTEP_STAMP_NSEC_STAMP_NSEC GENMASK(29, 0)
+#define PTP_PTP_TWOSTEP_STAMP_NSEC_STAMP_NSEC_SET(x)\
+ FIELD_PREP(PTP_PTP_TWOSTEP_STAMP_NSEC_STAMP_NSEC, x)
+#define PTP_PTP_TWOSTEP_STAMP_NSEC_STAMP_NSEC_GET(x)\
+ FIELD_GET(PTP_PTP_TWOSTEP_STAMP_NSEC_STAMP_NSEC, x)
+
+/* LAN969X ONLY */
+/* DEVCPU_PTP:PTP_TS_FIFO:PTP_TWOSTEP_STAMP_SUBNS */
+#define PTP_PTP_TWOSTEP_STAMP_SUBNS \
+ __REG(TARGET_PTP, 0, 1, 612, 0, 1, 16, 8, 0, 1, 4)
+
+#define PTP_PTP_TWOSTEP_STAMP_SUBNS_STAMP_SUB_NSEC GENMASK(7, 0)
+#define PTP_PTP_TWOSTEP_STAMP_SUBNS_STAMP_SUB_NSEC_SET(x)\
+ FIELD_PREP(PTP_PTP_TWOSTEP_STAMP_SUBNS_STAMP_SUB_NSEC, x)
+#define PTP_PTP_TWOSTEP_STAMP_SUBNS_STAMP_SUB_NSEC_GET(x)\
+ FIELD_GET(PTP_PTP_TWOSTEP_STAMP_SUBNS_STAMP_SUB_NSEC, x)
+
/* QFWD:SYSTEM:SWITCH_PORT_MODE */
#define QFWD_SWITCH_PORT_MODE(r) \
__REG(TARGET_QFWD, 0, 1, 0, 0, 1, 340, 0, r, \
--
2.34.1
next prev parent reply other threads:[~2024-10-21 13:59 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-10-21 13:58 [PATCH net-next 00/15] net: sparx5: add support for lan969x switch device Daniel Machon
2024-10-21 13:58 ` [PATCH net-next 01/15] net: sparx5: add support for lan969x SKU's and core clock Daniel Machon
2024-10-22 8:57 ` Simon Horman
2024-10-21 13:58 ` [PATCH net-next 02/15] net: sparx5: change spx5_wr to spx5_rmw in cal update() Daniel Machon
2024-10-21 13:58 ` [PATCH net-next 03/15] net: sparx5: change frequency calculation for SDLB's Daniel Machon
2024-10-21 13:58 ` [PATCH net-next 04/15] net: sparx5: add sparx5 context pointer to a few functions Daniel Machon
2024-10-21 13:58 ` Daniel Machon [this message]
2024-10-21 17:33 ` [PATCH net-next 05/15] net: sparx5: add registers required by lan969x Maxime Chevallier
2024-10-21 19:10 ` Daniel Machon
2024-10-21 13:58 ` [PATCH net-next 06/15] net: lan969x: add match data for lan969x Daniel Machon
2024-10-23 1:32 ` kernel test robot
2024-10-23 20:53 ` kernel test robot
2024-10-24 15:52 ` kernel test robot
2024-10-21 13:58 ` [PATCH net-next 07/15] net: lan969x: add register diffs to match data Daniel Machon
2024-10-21 13:58 ` [PATCH net-next 08/15] net: lan969x: add constants " Daniel Machon
2024-10-21 13:58 ` [PATCH net-next 09/15] net: lan969x: add lan969x ops " Daniel Machon
2024-10-21 13:58 ` [PATCH net-next 10/15] net: lan969x: add PTP handler function Daniel Machon
2024-10-21 17:46 ` Maxime Chevallier
2024-10-21 19:12 ` Daniel Machon
2024-10-21 13:58 ` [PATCH net-next 11/15] net: lan969x: add function for calculating the DSM calendar Daniel Machon
2024-10-21 17:51 ` Maxime Chevallier
2024-10-21 19:13 ` Daniel Machon
2024-10-21 13:58 ` [PATCH net-next 12/15] net: sparx5: use is_sparx5() macro throughout Daniel Machon
2024-10-21 13:58 ` [PATCH net-next 13/15] dt-bindings: net: add compatible strings for lan969x SKU's Daniel Machon
2024-10-22 6:11 ` Krzysztof Kozlowski
2024-10-21 13:58 ` [PATCH net-next 14/15] net: sparx5: add compatible strings for lan969x and verify the target Daniel Machon
2024-10-22 6:09 ` Krzysztof Kozlowski
2024-10-22 8:32 ` Daniel Machon
2024-10-22 8:50 ` Simon Horman
2024-10-22 12:08 ` Daniel Machon
2024-10-22 13:35 ` Simon Horman
2024-10-23 8:14 ` Krzysztof Kozlowski
2024-10-23 11:00 ` Daniel Machon
2024-10-23 12:06 ` Krzysztof Kozlowski
2024-10-23 18:33 ` Daniel Machon
2024-10-21 13:58 ` [PATCH net-next 15/15] net: sparx5: add feature support Daniel Machon
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20241021-sparx5-lan969x-switch-driver-2-v1-5-c8c49ef21e0f@microchip.com \
--to=daniel.machon@microchip.com \
--cc=Parthiban.Veerasooran@microchip.com \
--cc=Raju.Lakkaraju@microchip.com \
--cc=Steen.Hegelund@microchip.com \
--cc=UNGLinuxDriver@microchip.com \
--cc=andrew@lunn.ch \
--cc=ast@fiberby.net \
--cc=conor+dt@kernel.org \
--cc=davem@davemloft.net \
--cc=devicetree@vger.kernel.org \
--cc=edumazet@google.com \
--cc=horatiu.vultur@microchip.com \
--cc=jacob.e.keller@intel.com \
--cc=jensemil.schulzostergaard@microchip.com \
--cc=krzk+dt@kernel.org \
--cc=kuba@kernel.org \
--cc=lars.povlsen@microchip.com \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=maxime.chevallier@bootlin.com \
--cc=netdev@vger.kernel.org \
--cc=pabeni@redhat.com \
--cc=richardcochran@gmail.com \
--cc=robh@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).