* [PATCH 0/5] dts: qcom: Introduce SM8750 device trees
@ 2024-10-21 23:21 Melody Olvera
2024-10-21 23:21 ` [PATCH 1/5] dt-bindings: arm: qcom: Document sm8750 SoC and boards Melody Olvera
` (5 more replies)
0 siblings, 6 replies; 18+ messages in thread
From: Melody Olvera @ 2024-10-21 23:21 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Lee Jones, Catalin Marinas, Will Deacon,
Geert Uytterhoeven, Dmitry Baryshkov, AngeloGioacchino Del Regno,
Neil Armstrong, Arnd Bergmann, Nícolas F . R . A . Prado,
Stephen Boyd, Trilok Soni, Satya Durga Srinivasu Prabhala
Cc: linux-arm-msm, devicetree, linux-kernel, linux-arm-kernel,
Melody Olvera
This series adds the initial device tree support for the SM8750 SoCs
needed to boot to shell. This specifically adds support for clocks,
pinctrl, rpmhpd, regulators, interconnects, and SoC and board
compatibles.
The Qualcomm Technologies, Inc. SM8750 SoC is the latest in the line of
consumer mobile device SoCs. See more at:
https://www.qualcomm.com/content/dam/qcomm-martech/dm-assets/images/company/news-media/media-center/press-kits/snapdragon-summit-2024/day-1/documents/Snapdragon8EliteProductBrief.pdf
Dependencies:
clks: https://lore.kernel.org/all/20241021230359.2632414-1-quic_molvera@quicinc.com/
interconnects: https://lore.kernel.org/all/20241021231823.2635534-1-quic_molvera@quicinc.com/
pinctrl: https://lore.kernel.org/all/20241021230414.2632428-1-quic_molvera@quicinc.com/
regulators: https://lore.kernel.org/all/20241021230348.2632381-1-quic_molvera@quicinc.com/
power domains: https://lore.kernel.org/all/20241021230333.2632368-1-quic_molvera@quicinc.com/
misc bindings:
- https://lore.kernel.org/all/20241021230427.2632466-1-quic_molvera@quicinc.com/
- https://lore.kernel.org/all/20241021230500.2632527-1-quic_molvera@quicinc.com/
- https://lore.kernel.org/all/20241021230439.2632480-1-quic_molvera@quicinc.com/
- https://lore.kernel.org/all/20241021230449.2632493-1-quic_molvera@quicinc.com/
Jishnu Prakash (2):
dt-bindings: mfd: qcom,spmi-pmic: Document PMICs added in SM8750
arm64: dts: qcom: Add pmd8028 and pmih0108 PMIC dtsi files
Melody Olvera (3):
dt-bindings: arm: qcom: Document sm8750 SoC and boards
arm64: dts: qcom: Add base sm8750 dtsi and mtp and qrd dts
arm64: defconfig: Enable SM8750 SoC base configs
.../devicetree/bindings/arm/qcom.yaml | 7 +
.../bindings/mfd/qcom,spmi-pmic.yaml | 2 +
arch/arm64/boot/dts/qcom/Makefile | 2 +
arch/arm64/boot/dts/qcom/pmd8028.dtsi | 56 +
arch/arm64/boot/dts/qcom/pmih0108.dtsi | 62 +
arch/arm64/boot/dts/qcom/sm8750-mtp.dts | 968 ++++++
arch/arm64/boot/dts/qcom/sm8750-qrd.dts | 965 ++++++
arch/arm64/boot/dts/qcom/sm8750.dtsi | 2903 +++++++++++++++++
arch/arm64/configs/defconfig | 4 +
9 files changed, 4969 insertions(+)
create mode 100644 arch/arm64/boot/dts/qcom/pmd8028.dtsi
create mode 100644 arch/arm64/boot/dts/qcom/pmih0108.dtsi
create mode 100644 arch/arm64/boot/dts/qcom/sm8750-mtp.dts
create mode 100644 arch/arm64/boot/dts/qcom/sm8750-qrd.dts
create mode 100644 arch/arm64/boot/dts/qcom/sm8750.dtsi
base-commit: 63b3ff03d91ae8f875fe8747c781a521f78cde17
prerequisite-patch-id: 5a4ad7a91dffc1c63a6513736cab88404937bbc5
prerequisite-patch-id: f98e160b22d065fef3919e807102619ef80a63fd
prerequisite-patch-id: 9df63975d51d61db536e843f261f837de613c0bb
prerequisite-patch-id: dca6974344b25b6160e6a2680c438bc59da33374
prerequisite-patch-id: 36ad7b3a06074897abcbe9521452ed0ec632e2eb
prerequisite-patch-id: 255b9f24b2765ad6bb8fd5213b620ba2263d48f7
prerequisite-patch-id: f458aa6a3d53924449be96609a0d1e65ec9f4854
prerequisite-patch-id: 5bc1ec8226b52170508fd5ac30e31fec72e86f5a
prerequisite-patch-id: 2b556803a12148cc12c1edcb5e143a454679a047
prerequisite-patch-id: 0924872ce84c0f0011d53e98e58bf61213e9df43
prerequisite-patch-id: 3a6538f98c3ce876d8acf3a0c55ac04897cfaf43
prerequisite-patch-id: 7e047c63eff592833642eae37492b09e1ea7ed2d
prerequisite-patch-id: cf8bef95f79c460b5b1c231a1122aa0173807a4d
prerequisite-patch-id: ba4dd339acd73f885fe3d5f018ac620997583599
prerequisite-patch-id: 5b930049e39fbd1ace2562d7870c2af764fe4cd4
prerequisite-patch-id: 58acef79b9bf6c2e7d69d598d24502787eddc910
prerequisite-patch-id: 369d52ee563f34eeca4a9c36e6d2b36b24eac635
prerequisite-patch-id: e02a35925d37a2e61abbf240cc8963208f54e1c0
prerequisite-patch-id: e4bf91d9a22d34c567eeab5b0f6fb90913ee908b
--
2.46.1
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH 1/5] dt-bindings: arm: qcom: Document sm8750 SoC and boards
2024-10-21 23:21 [PATCH 0/5] dts: qcom: Introduce SM8750 device trees Melody Olvera
@ 2024-10-21 23:21 ` Melody Olvera
2024-10-23 8:29 ` Krzysztof Kozlowski
2024-10-21 23:21 ` [PATCH 2/5] dt-bindings: mfd: qcom,spmi-pmic: Document PMICs added in SM8750 Melody Olvera
` (4 subsequent siblings)
5 siblings, 1 reply; 18+ messages in thread
From: Melody Olvera @ 2024-10-21 23:21 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Lee Jones, Catalin Marinas, Will Deacon,
Geert Uytterhoeven, Dmitry Baryshkov, AngeloGioacchino Del Regno,
Neil Armstrong, Arnd Bergmann, Nícolas F . R . A . Prado,
Stephen Boyd, Trilok Soni, Satya Durga Srinivasu Prabhala
Cc: linux-arm-msm, devicetree, linux-kernel, linux-arm-kernel,
Melody Olvera
Document the SM8750 SoC binding and the boards which use it.
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
---
Documentation/devicetree/bindings/arm/qcom.yaml | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml
index 0d451082570e..552c0f725dac 100644
--- a/Documentation/devicetree/bindings/arm/qcom.yaml
+++ b/Documentation/devicetree/bindings/arm/qcom.yaml
@@ -82,6 +82,7 @@ description: |
sm8450
sm8550
sm8650
+ sm8750
x1e80100
There are many devices in the list below that run the standard ChromeOS
@@ -1050,6 +1051,12 @@ properties:
- qcom,sm8650-qrd
- const: qcom,sm8650
+ - items:
+ - enum:
+ - qcom,sm8750-mtp
+ - qcom,sm8750-qrd
+ - const: qcom,sm8750
+
- items:
- enum:
- lenovo,thinkpad-t14s
--
2.46.1
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 2/5] dt-bindings: mfd: qcom,spmi-pmic: Document PMICs added in SM8750
2024-10-21 23:21 [PATCH 0/5] dts: qcom: Introduce SM8750 device trees Melody Olvera
2024-10-21 23:21 ` [PATCH 1/5] dt-bindings: arm: qcom: Document sm8750 SoC and boards Melody Olvera
@ 2024-10-21 23:21 ` Melody Olvera
2024-10-23 8:30 ` Krzysztof Kozlowski
2024-11-01 15:56 ` (subset) " Lee Jones
2024-10-21 23:21 ` [PATCH 3/5] arm64: dts: qcom: Add pmd8028 and pmih0108 PMIC dtsi files Melody Olvera
` (3 subsequent siblings)
5 siblings, 2 replies; 18+ messages in thread
From: Melody Olvera @ 2024-10-21 23:21 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Lee Jones, Catalin Marinas, Will Deacon,
Geert Uytterhoeven, Dmitry Baryshkov, AngeloGioacchino Del Regno,
Neil Armstrong, Arnd Bergmann, Nícolas F . R . A . Prado,
Stephen Boyd, Trilok Soni, Satya Durga Srinivasu Prabhala
Cc: linux-arm-msm, devicetree, linux-kernel, linux-arm-kernel,
Jishnu Prakash, Melody Olvera
From: Jishnu Prakash <quic_jprakash@quicinc.com>
Document compatibles for the added pmd8028 and pmih0108 SPMI PMICs.
Signed-off-by: Jishnu Prakash <quic_jprakash@quicinc.com>
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
---
Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml b/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml
index a2b2fbf77d5c..078a6886f8b1 100644
--- a/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml
+++ b/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml
@@ -76,12 +76,14 @@ properties:
- qcom,pmc8180
- qcom,pmc8180c
- qcom,pmc8380
+ - qcom,pmd8028
- qcom,pmd9635
- qcom,pmi632
- qcom,pmi8950
- qcom,pmi8962
- qcom,pmi8994
- qcom,pmi8998
+ - qcom,pmih0108
- qcom,pmk8002
- qcom,pmk8350
- qcom,pmk8550
--
2.46.1
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 3/5] arm64: dts: qcom: Add pmd8028 and pmih0108 PMIC dtsi files
2024-10-21 23:21 [PATCH 0/5] dts: qcom: Introduce SM8750 device trees Melody Olvera
2024-10-21 23:21 ` [PATCH 1/5] dt-bindings: arm: qcom: Document sm8750 SoC and boards Melody Olvera
2024-10-21 23:21 ` [PATCH 2/5] dt-bindings: mfd: qcom,spmi-pmic: Document PMICs added in SM8750 Melody Olvera
@ 2024-10-21 23:21 ` Melody Olvera
2024-10-21 23:21 ` [PATCH 4/5] arm64: dts: qcom: Add base sm8750 dtsi and mtp and qrd dts Melody Olvera
` (2 subsequent siblings)
5 siblings, 0 replies; 18+ messages in thread
From: Melody Olvera @ 2024-10-21 23:21 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Lee Jones, Catalin Marinas, Will Deacon,
Geert Uytterhoeven, Dmitry Baryshkov, AngeloGioacchino Del Regno,
Neil Armstrong, Arnd Bergmann, Nícolas F . R . A . Prado,
Stephen Boyd, Trilok Soni, Satya Durga Srinivasu Prabhala
Cc: linux-arm-msm, devicetree, linux-kernel, linux-arm-kernel,
Jishnu Prakash, Melody Olvera
From: Jishnu Prakash <quic_jprakash@quicinc.com>
Add dtsi files for pmd8028 and pmih0108 PMICs, used on SM8750
platforms.
Signed-off-by: Jishnu Prakash <quic_jprakash@quicinc.com>
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
---
arch/arm64/boot/dts/qcom/pmd8028.dtsi | 56 +++++++++++++++++++++++
arch/arm64/boot/dts/qcom/pmih0108.dtsi | 62 ++++++++++++++++++++++++++
2 files changed, 118 insertions(+)
create mode 100644 arch/arm64/boot/dts/qcom/pmd8028.dtsi
create mode 100644 arch/arm64/boot/dts/qcom/pmih0108.dtsi
diff --git a/arch/arm64/boot/dts/qcom/pmd8028.dtsi b/arch/arm64/boot/dts/qcom/pmd8028.dtsi
new file mode 100644
index 000000000000..f8ef8e133854
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/pmd8028.dtsi
@@ -0,0 +1,56 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/spmi/spmi.h>
+
+/ {
+ thermal-zones {
+ pmd8028-thermal {
+ polling-delay-passive = <100>;
+ thermal-sensors = <&pmd8028_temp_alarm>;
+
+ trips {
+ pmd8028_trip0: trip0 {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ pmd8028_trip1: trip1 {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "hot";
+ };
+ };
+ };
+ };
+};
+
+&spmi_bus {
+ pmd8028: pmic@4 {
+ compatible = "qcom,pmd8028", "qcom,spmi-pmic";
+ reg = <0x4 SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pmd8028_temp_alarm: temp-alarm@a00 {
+ compatible = "qcom,spmi-temp-alarm";
+ reg = <0xa00>;
+ interrupts = <0x4 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
+ #thermal-sensor-cells = <0>;
+ };
+
+ pmd8028_gpios: gpio@8800 {
+ compatible = "qcom,pmd8028-gpio", "qcom,spmi-gpio";
+ reg = <0x8800>;
+ gpio-controller;
+ gpio-ranges = <&pmd8028_gpios 0 0 4>;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/qcom/pmih0108.dtsi b/arch/arm64/boot/dts/qcom/pmih0108.dtsi
new file mode 100644
index 000000000000..c868ebf77213
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/pmih0108.dtsi
@@ -0,0 +1,62 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/spmi/spmi.h>
+
+/ {
+ thermal-zones {
+ pmih0108-thermal {
+ polling-delay-passive = <100>;
+ thermal-sensors = <&pmih0108_temp_alarm>;
+
+ trips {
+ trip0 {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ trip1 {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "hot";
+ };
+ };
+ };
+ };
+};
+
+&spmi_bus {
+ pmih0108: pmic@7 {
+ compatible = "qcom,pmih0108", "qcom,spmi-pmic";
+ reg = <0x7 SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pmih0108_temp_alarm: temp-alarm@a00 {
+ compatible = "qcom,spmi-temp-alarm";
+ reg = <0xa00>;
+ interrupts = <0x7 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
+ #thermal-sensor-cells = <0>;
+ };
+
+ pmih0108_gpios: gpio@8800 {
+ compatible = "qcom,pmih0108-gpio", "qcom,spmi-gpio";
+ reg = <0x8800>;
+ gpio-controller;
+ gpio-ranges = <&pmih0108_gpios 0 0 18>;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ pmih0108_eusb2_repeater: eusb2-repeater@fd00 {
+ compatible = "qcom,pm8550b-eusb2-repeater";
+ reg = <0xfd00>;
+ #phy-cells = <0>;
+ };
+ };
+};
--
2.46.1
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 4/5] arm64: dts: qcom: Add base sm8750 dtsi and mtp and qrd dts
2024-10-21 23:21 [PATCH 0/5] dts: qcom: Introduce SM8750 device trees Melody Olvera
` (2 preceding siblings ...)
2024-10-21 23:21 ` [PATCH 3/5] arm64: dts: qcom: Add pmd8028 and pmih0108 PMIC dtsi files Melody Olvera
@ 2024-10-21 23:21 ` Melody Olvera
2024-10-23 3:12 ` Bjorn Andersson
2024-11-02 9:36 ` Konrad Dybcio
2024-10-21 23:21 ` [PATCH 5/5] arm64: defconfig: Enable SM8750 SoC base configs Melody Olvera
2024-10-24 16:33 ` [PATCH 0/5] dts: qcom: Introduce SM8750 device trees Rob Herring (Arm)
5 siblings, 2 replies; 18+ messages in thread
From: Melody Olvera @ 2024-10-21 23:21 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Lee Jones, Catalin Marinas, Will Deacon,
Geert Uytterhoeven, Dmitry Baryshkov, AngeloGioacchino Del Regno,
Neil Armstrong, Arnd Bergmann, Nícolas F . R . A . Prado,
Stephen Boyd, Trilok Soni, Satya Durga Srinivasu Prabhala
Cc: linux-arm-msm, devicetree, linux-kernel, linux-arm-kernel,
Melody Olvera, Taniya Das, Jishnu Prakash, Raviteja Laggyshetty
Add base dtsi for the sm8750 SoC describing the CPUs, GCC and
RPMHCC clock controllers, geni UART, interrupt controller, TLMM,
reserved memory, interconnects, regulator, and SMMU nodes. Also add
MTP and QRD board dts files for sm8750.
Co-developed-by: Taniya Das <quic_tdas@quicinc.com>
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Co-developed-by: Jishnu Prakash <quic_jprakash@quicinc.com>
Signed-off-by: Jishnu Prakash <quic_jprakash@quicinc.com>
Co-developed-by: Raviteja Laggyshetty <quic_rlaggysh@quicinc.com>
Signed-off-by: Raviteja Laggyshetty <quic_rlaggysh@quicinc.com>
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
---
arch/arm64/boot/dts/qcom/Makefile | 2 +
arch/arm64/boot/dts/qcom/sm8750-mtp.dts | 968 ++++++++
arch/arm64/boot/dts/qcom/sm8750-qrd.dts | 965 ++++++++
arch/arm64/boot/dts/qcom/sm8750.dtsi | 2903 +++++++++++++++++++++++
4 files changed, 4838 insertions(+)
create mode 100644 arch/arm64/boot/dts/qcom/sm8750-mtp.dts
create mode 100644 arch/arm64/boot/dts/qcom/sm8750-qrd.dts
create mode 100644 arch/arm64/boot/dts/qcom/sm8750.dtsi
diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
index 065bb19481c1..3bedfa6b37f2 100644
--- a/arch/arm64/boot/dts/qcom/Makefile
+++ b/arch/arm64/boot/dts/qcom/Makefile
@@ -269,6 +269,8 @@ dtb-$(CONFIG_ARCH_QCOM) += sm8650-hdk-display-card.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8650-hdk.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8650-mtp.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8650-qrd.dtb
+dtb-$(CONFIG_ARCH_QCOM) += sm8750-mtp.dtb
+dtb-$(CONFIG_ARCH_QCOM) += sm8750-qrd.dtb
dtb-$(CONFIG_ARCH_QCOM) += x1e78100-lenovo-thinkpad-t14s.dtb
dtb-$(CONFIG_ARCH_QCOM) += x1e80100-asus-vivobook-s15.dtb
dtb-$(CONFIG_ARCH_QCOM) += x1e80100-crd.dtb
diff --git a/arch/arm64/boot/dts/qcom/sm8750-mtp.dts b/arch/arm64/boot/dts/qcom/sm8750-mtp.dts
new file mode 100644
index 000000000000..e1a94dc76e2f
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sm8750-mtp.dts
@@ -0,0 +1,968 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
+#include "sm8750.dtsi"
+#include "pm8010.dtsi"
+#include "pm8550.dtsi"
+#define PMK8550VE_SID 8
+#include "pm8550ve.dtsi"
+#include "pmd8028.dtsi"
+#include "pmih0108.dtsi"
+#include "pmk8550.dtsi"
+#include "pmr735d_a.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. SM8750 MTP";
+ compatible = "qcom,sm8750-mtp", "qcom,sm8750";
+
+ aliases {
+ serial0 = &uart7;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ clocks {
+ xo_board: xo-board {
+ compatible = "fixed-clock";
+ clock-frequency = <76800000>;
+ #clock-cells = <0>;
+ };
+
+ sleep_clk: sleep-clk {
+ compatible = "fixed-clock";
+ clock-frequency = <32000>;
+ #clock-cells = <0>;
+ };
+
+ bi_tcxo: bi-tcxo-clk {
+ compatible = "fixed-factor-clock";
+ #clock-cells = <0>;
+
+ clocks = <&rpmhcc RPMH_CXO_PAD_CLK>;
+ clock-mult = <1>;
+ clock-div = <2>;
+ };
+
+ bi_tcxo_ao: bi-tcxo-ao-clk {
+ compatible = "fixed-factor-clock";
+ #clock-cells = <0>;
+
+ clocks = <&rpmhcc RPMH_CXO_PAD_CLK_A>;
+ clock-mult = <1>;
+ clock-div = <2>;
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ pinctrl-0 = <&volume_up_n>;
+ pinctrl-names = "default";
+
+ key-volume-up {
+ label = "Volume Up";
+ linux,code = <KEY_VOLUMEUP>;
+ gpios = <&pm8550_gpios 6 GPIO_ACTIVE_LOW>;
+ debounce-interval = <15>;
+ linux,can-disable;
+ wakeup-source;
+ };
+ };
+
+ thermal-zones {
+ pm8550ve-d-thermal {
+ polling-delay-passive = <100>;
+
+ thermal-sensors = <&pm8550ve_d_temp_alarm>;
+
+ trips {
+ trip0 {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ trip1 {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "hot";
+ };
+ };
+ };
+
+ pm8550ve-f-thermal {
+ polling-delay-passive = <100>;
+
+ thermal-sensors = <&pm8550ve_f_temp_alarm>;
+
+ trips {
+ trip0 {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ trip1 {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "hot";
+ };
+ };
+ };
+
+ pm8550ve-g-thermal {
+ polling-delay-passive = <100>;
+
+ thermal-sensors = <&pm8550ve_g_temp_alarm>;
+
+ trips {
+ trip0 {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ trip1 {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "hot";
+ };
+ };
+ };
+
+ pm8550vs-j-thermal {
+ polling-delay-passive = <100>;
+
+ thermal-sensors = <&pm8550vs_j_temp_alarm>;
+
+ trips {
+ trip0 {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ trip1 {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "hot";
+ };
+ };
+ };
+ };
+
+ vph_pwr: vph-pwr-regulator {
+ compatible = "regulator-fixed";
+
+ regulator-name = "vph_pwr";
+ regulator-min-microvolt = <3700000>;
+ regulator-max-microvolt = <3700000>;
+
+ regulator-always-on;
+ regulator-boot-on;
+ };
+};
+
+&apps_rsc {
+ regulators-0 {
+ compatible = "qcom,pm8550-rpmh-regulators";
+
+ vdd-bob1-supply = <&vph_pwr>;
+ vdd-bob2-supply = <&vph_pwr>;
+ vdd-l1-supply = <&vreg_s3g_1p8>;
+ vdd-l2-l13-l14-supply = <&vreg_bob1>;
+ vdd-l3-supply = <&vreg_s7i_1p2>;
+ vdd-l4-supply = <&vreg_s3g_1p8>;
+ vdd-l5-l16-supply = <&vreg_bob1>;
+ vdd-l6-l7-supply = <&vreg_bob1>;
+ vdd-l8-l9-supply = <&vreg_bob1>;
+ vdd-l10-supply = <&vreg_s3g_1p8>;
+ vdd-l11-supply = <&vreg_s7i_1p2>;
+ vdd-l12-supply = <&vreg_s3g_1p8>;
+ vdd-l15-supply = <&vreg_s3g_1p8>;
+ vdd-l17-supply = <&vreg_bob2>;
+
+ qcom,pmic-id = "b";
+
+ vreg_bob1: bob1 {
+ regulator-name = "vreg_bob1";
+ regulator-min-microvolt = <3008000>;
+ regulator-max-microvolt = <4000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_bob2: bob2 {
+ regulator-name = "vreg_bob2";
+ regulator-min-microvolt = <2704000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l1b_1p8: ldo1 {
+ regulator-name = "vreg_l1b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2b_3p0: ldo2 {
+ regulator-name = "vreg_l2b_3p0";
+ regulator-min-microvolt = <3008000>;
+ regulator-max-microvolt = <3048000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l4b_1p8: ldo4 {
+ regulator-name = "vreg_l4b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l5b_3p1: ldo5 {
+ regulator-name = "vreg_l5b_3p1";
+ regulator-min-microvolt = <3100000>;
+ regulator-max-microvolt = <3148000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l6b_1p8: ldo6 {
+ regulator-name = "vreg_l6b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l7b_1p8: ldo7 {
+ regulator-name = "vreg_l7b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+
+ };
+
+ vreg_l8b_1p8: ldo8 {
+ regulator-name = "vreg_l8b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l9b_2p9: ldo9 {
+ regulator-name = "vreg_l9b_2p9";
+ regulator-min-microvolt = <2960000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l10b_1p8: ldo10 {
+ regulator-name = "vreg_l10b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l11b_1p0: ldo11 {
+ regulator-name = "vreg_l11b_1p0";
+ regulator-min-microvolt = <1064000>;
+ regulator-max-microvolt = <1292000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l12b_1p8: ldo12 {
+ regulator-name = "vreg_l12b_1p8";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l13b_3p0: ldo13 {
+ regulator-name = "vreg_l13b_3p0";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l14b_3p2: ldo14 {
+ regulator-name = "vreg_l14b_3p2";
+ regulator-min-microvolt = <3200000>;
+ regulator-max-microvolt = <3200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l15b_1p8: ldo15 {
+ regulator-name = "vreg_l15b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l16b_2p8: ldo16 {
+ regulator-name = "vreg_l16b_2p8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l17b_2p5: ldo17 {
+ regulator-name = "vreg_l17b_2p5";
+ regulator-min-microvolt = <2504000>;
+ regulator-max-microvolt = <2504000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-1 {
+ compatible = "qcom,pm8550ve-rpmh-regulators";
+
+ vdd-l1-supply = <&vreg_s7i_1p2>;
+ vdd-l2-supply = <&vreg_s1d_0p97>;
+ vdd-l3-supply = <&vreg_s1d_0p97>;
+ vdd-s1-supply = <&vph_pwr>;
+ vdd-s3-supply = <&vph_pwr>;
+ vdd-s4-supply = <&vph_pwr>;
+
+ qcom,pmic-id = "d";
+
+ vreg_s1d_0p97: smps1 {
+ regulator-name = "vreg_s1d_0p97";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s3d_1p2: smps3 {
+ regulator-name = "vreg_s3d_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s4d_0p85: smps4 {
+ regulator-name = "vreg_s4d_0p85";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1036000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l1d_1p2: ldo1 {
+ regulator-name = "vreg_l1d_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2d_0p88: ldo2 {
+ regulator-name = "vreg_l2d_0p88";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <912000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3d_0p88: ldo3 {
+ regulator-name = "vreg_l3d_0p88";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <920000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-2 {
+ compatible = "qcom,pm8550ve-rpmh-regulators";
+
+ vdd-l1-supply = <&vreg_s1d_0p97>;
+ vdd-l2-supply = <&vreg_s7i_1p2>;
+ vdd-l3-supply = <&vreg_s3g_1p8>;
+ vdd-s5-supply = <&vph_pwr>;
+
+ qcom,pmic-id = "f";
+
+ vreg_s5f_0p5: smps5 {
+ regulator-name = "vreg_s5f_0p5";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l1f_0p88: ldo1 {
+ regulator-name = "vreg_l1f_0p88";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <920000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2f_1p2: ldo2 {
+ regulator-name = "vreg_l2f_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3f_1p8: ldo3 {
+ regulator-name = "vreg_l3f_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ };
+
+ regulators-3 {
+ compatible = "qcom,pm8550ve-rpmh-regulators";
+
+ vdd-l1-supply = <&vreg_s1d_0p97>;
+ vdd-l2-supply = <&vreg_s3g_1p8>;
+ vdd-l3-supply = <&vreg_s7i_1p2>;
+ vdd-s1-supply = <&vph_pwr>;
+ vdd-s3-supply = <&vph_pwr>;
+
+ qcom,pmic-id = "g";
+
+ vreg_s1g_0p5: smps1 {
+ regulator-name = "vreg_s1g_0p5";
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <700000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s3g_1p8: smps3 {
+ regulator-name = "vreg_s3g_1p8";
+ regulator-min-microvolt = <1856000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s4g_0p75: smps4 {
+ regulator-name = "vreg_s4g_0p75";
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <900000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l1g_0p91: ldo1 {
+ regulator-name = "vreg_l1g_0p91";
+ regulator-min-microvolt = <912000>;
+ regulator-max-microvolt = <936000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2g_1p8: ldo2 {
+ regulator-name = "vreg_l2g_1p8";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1860000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3g_1p2: ldo3 {
+ regulator-name = "vreg_l3g_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1256000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-4 {
+ compatible = "qcom,pm8550ve-rpmh-regulators";
+
+ vdd-l1-supply = <&vreg_s7i_1p2>;
+ vdd-l2-supply = <&vreg_s7i_1p2>;
+ vdd-l3-supply = <&vreg_s1d_0p97>;
+ vdd-s7-supply = <&vph_pwr>;
+ vdd-s8-supply = <&vph_pwr>;
+
+ qcom,pmic-id = "i";
+
+ vreg_s7i_1p2: smps7 {
+ regulator-name = "vreg_s7i_1p2";
+ regulator-min-microvolt = <1224000>;
+ regulator-max-microvolt = <1340000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s8i_0p9: smps8 {
+ regulator-name = "vreg_s8i_0p9";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <972000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l1i_1p2: ldo1 {
+ regulator-name = "vreg_l1i_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2i_1p2: ldo2 {
+ regulator-name = "vreg_l2i_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3i_0p88: ldo3 {
+ regulator-name = "vreg_l3i_0p88";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <912000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-5 {
+ compatible = "qcom,pm8550vs-rpmh-regulators";
+
+ vdd-l1-supply = <&vreg_s1d_0p97>;
+ vdd-l2-supply = <&vreg_s7i_1p2>;
+ vdd-s2-supply = <&vph_pwr>;
+ vdd-s3-supply = <&vph_pwr>;
+ vdd-s4-supply = <&vph_pwr>;
+
+ qcom,pmic-id = "j";
+
+ vreg_s2j_1p1: smps2 {
+ regulator-name = "vreg_s2j_1p1";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s3j_1p1: smps3 {
+ regulator-name = "vreg_s3j_1p1";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l1j_0p91: ldo1 {
+ regulator-name = "vreg_l1j_0p91";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <920000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2j_1p2: ldo2 {
+ regulator-name = "vreg_l2j_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-6 {
+ compatible = "qcom,pm8010-rpmh-regulators";
+ qcom,pmic-id = "m";
+
+ vdd-l1-l2-supply = <&vreg_s7i_1p2>;
+ vdd-l3-l4-supply = <&vreg_bob2>;
+ vdd-l5-supply = <&vreg_s3g_1p8>;
+ vdd-l6-supply = <&vreg_bob1>;
+ vdd-l7-supply = <&vreg_bob1>;
+
+ vreg_l1m_1p1: ldo1 {
+ regulator-name = "vreg_l1m_1p1";
+ regulator-min-microvolt = <1104000>;
+ regulator-max-microvolt = <1104000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2m_1p056: ldo2 {
+ regulator-name = "vreg_l2m_1p056";
+ regulator-min-microvolt = <1056000>;
+ regulator-max-microvolt = <1056000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3m_2p8: ldo3 {
+ regulator-name = "vreg_l3m_2p8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l4m_2p8: ldo4 {
+ regulator-name = "vreg_l4m_2p8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l5m_1p8: ldo5 {
+ regulator-name = "vreg_l5m_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l6m_2p8: ldo6 {
+ regulator-name = "vreg_l6m_2p8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l7m_2p96: ldo7 {
+ regulator-name = "vreg_l7m_2p96";
+ regulator-min-microvolt = <2960000>;
+ regulator-max-microvolt = <2960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-7 {
+ compatible = "qcom,pm8010-rpmh-regulators";
+ qcom,pmic-id = "n";
+
+ vdd-l1-l2-supply = <&vreg_s7i_1p2>;
+ vdd-l3-l4-supply = <&vreg_s3g_1p8>;
+ vdd-l5-supply = <&vreg_bob2>;
+ vdd-l6-supply = <&vreg_bob2>;
+ vdd-l7-supply = <&vreg_bob1>;
+
+ vreg_l1n_1p1: ldo1 {
+ regulator-name = "vreg_l1n_1p1";
+ regulator-min-microvolt = <1104000>;
+ regulator-max-microvolt = <1104000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2n_1p1: ldo2 {
+ regulator-name = "vreg_l2n_1p1";
+ regulator-min-microvolt = <1104000>;
+ regulator-max-microvolt = <1104000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3n_1p8: ldo3 {
+ regulator-name = "vreg_l3n_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l4n_1p8: ldo4 {
+ regulator-name = "vreg_l4n_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l5n_2p8: ldo5 {
+ regulator-name = "vreg_l5n_2p8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l6n_2p8: ldo6 {
+ regulator-name = "vreg_l6n_2p8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l7n_3p3: ldo7 {
+ regulator-name = "vreg_l7n_3p3";
+ regulator-min-microvolt = <3304000>;
+ regulator-max-microvolt = <3304000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+};
+
+&pm8550_flash {
+ status = "okay";
+
+ led-0 {
+ function = LED_FUNCTION_FLASH;
+ color = <LED_COLOR_ID_YELLOW>;
+ led-sources = <1>, <4>;
+ led-max-microamp = <500000>;
+ flash-max-microamp = <2000000>;
+ flash-max-timeout-us = <1280000>;
+ function-enumerator = <0>;
+ };
+
+ led-1 {
+ function = LED_FUNCTION_FLASH;
+ color = <LED_COLOR_ID_WHITE>;
+ led-sources = <2>, <3>;
+ led-max-microamp = <500000>;
+ flash-max-microamp = <2000000>;
+ flash-max-timeout-us = <1280000>;
+ function-enumerator = <1>;
+ };
+};
+
+&pm8550_gpios {
+ volume_up_n: volume-up-n-state {
+ pins = "gpio6";
+ function = "normal";
+ bias-pull-up;
+ input-enable;
+ power-source = <1>;
+ };
+};
+
+&pm8550_pwm {
+ status = "okay";
+
+ multi-led {
+ color = <LED_COLOR_ID_RGB>;
+ function = LED_FUNCTION_STATUS;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ led@1 {
+ reg = <1>;
+ color = <LED_COLOR_ID_RED>;
+ };
+
+ led@2 {
+ reg = <2>;
+ color = <LED_COLOR_ID_GREEN>;
+ };
+
+ led@3 {
+ reg = <3>;
+ color = <LED_COLOR_ID_BLUE>;
+ };
+ };
+};
+
+&pon_pwrkey {
+ status = "okay";
+};
+
+&pon_resin {
+ linux,code = <KEY_VOLUMEDOWN>;
+
+ status = "okay";
+};
+
+&pmih0108_eusb2_repeater {
+ status = "okay";
+
+ vdd18-supply = <&vreg_l15b_1p8>;
+ vdd3-supply = <&vreg_l5b_3p1>;
+};
+
+&qupv3_1 {
+ status = "okay";
+};
+
+&spmi_bus {
+ pm8550ve_d: pmic@3 {
+ compatible = "qcom,pm8550ve", "qcom,spmi-pmic";
+ reg = <0x3 SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pm8550ve_d_temp_alarm: temp-alarm@a00 {
+ compatible = "qcom,spmi-temp-alarm";
+ reg = <0xa00>;
+ interrupts = <0x3 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
+ #thermal-sensor-cells = <0>;
+ };
+
+ pm8550ve_d_gpios: gpio@8800 {
+ compatible = "qcom,pm8550ve-gpio", "qcom,spmi-gpio";
+ reg = <0x8800>;
+ gpio-controller;
+ gpio-ranges = <&pm8550ve_d_gpios 0 0 8>;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ pm8550ve_f: pmic@5 {
+ compatible = "qcom,pm8550ve", "qcom,spmi-pmic";
+ reg = <0x5 SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pm8550ve_f_temp_alarm: temp-alarm@a00 {
+ compatible = "qcom,spmi-temp-alarm";
+ reg = <0xa00>;
+ interrupts = <0x5 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
+ #thermal-sensor-cells = <0>;
+ };
+
+ pm8550ve_f_gpios: gpio@8800 {
+ compatible = "qcom,pm8550ve-gpio", "qcom,spmi-gpio";
+ reg = <0x8800>;
+ gpio-controller;
+ gpio-ranges = <&pm8550ve_f_gpios 0 0 6>;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ pm8550ve_g: pmic@6 {
+ compatible = "qcom,pm8550ve", "qcom,spmi-pmic";
+ reg = <0x6 SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pm8550ve_g_temp_alarm: temp-alarm@a00 {
+ compatible = "qcom,spmi-temp-alarm";
+ reg = <0xa00>;
+ interrupts = <0x6 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
+ #thermal-sensor-cells = <0>;
+ };
+
+ pm8550ve_g_gpios: gpio@8800 {
+ compatible = "qcom,pm8550ve-gpio", "qcom,spmi-gpio";
+ reg = <0x8800>;
+ gpio-controller;
+ gpio-ranges = <&pm8550ve_g_gpios 0 0 8>;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ pm8550vs_j: pmic@9 {
+ compatible = "qcom,pm8550vs", "qcom,spmi-pmic";
+ reg = <0x9 SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pm8550vs_j_temp_alarm: temp-alarm@a00 {
+ compatible = "qcom,spmi-temp-alarm";
+ reg = <0xa00>;
+ interrupts = <0x9 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
+ #thermal-sensor-cells = <0>;
+ };
+
+ pm8550vs_j_gpios: gpio@8800 {
+ compatible = "qcom,pm8550vs-gpio", "qcom,spmi-gpio";
+ reg = <0x8800>;
+ gpio-controller;
+ gpio-ranges = <&pm8550vs_j_gpios 0 0 6>;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+};
+
+&uart7 {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/qcom/sm8750-qrd.dts b/arch/arm64/boot/dts/qcom/sm8750-qrd.dts
new file mode 100644
index 000000000000..af0174d95e3a
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sm8750-qrd.dts
@@ -0,0 +1,965 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
+#include "sm8750.dtsi"
+#include "pm8010.dtsi"
+#include "pm8550.dtsi"
+#define PMK8550VE_SID 8
+#include "pm8550ve.dtsi"
+#include "pmd8028.dtsi"
+#include "pmih0108.dtsi"
+#include "pmk8550.dtsi"
+#include "pmr735d_a.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. SM8750 QRD";
+ compatible = "qcom,sm8750-qrd", "qcom,sm8750";
+
+ aliases {
+ serial0 = &uart7;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ clocks {
+ xo_board: xo-board {
+ compatible = "fixed-clock";
+ clock-frequency = <76800000>;
+ #clock-cells = <0>;
+ };
+
+ sleep_clk: sleep-clk {
+ compatible = "fixed-clock";
+ clock-frequency = <32000>;
+ #clock-cells = <0>;
+ };
+
+ bi_tcxo: bi-tcxo-clk {
+ compatible = "fixed-factor-clock";
+ #clock-cells = <0>;
+
+ clocks = <&rpmhcc RPMH_CXO_PAD_CLK>;
+ clock-mult = <1>;
+ clock-div = <2>;
+ };
+
+ bi_tcxo_ao: bi-tcxo-ao-clk {
+ compatible = "fixed-factor-clock";
+ #clock-cells = <0>;
+
+ clocks = <&rpmhcc RPMH_CXO_PAD_CLK_A>;
+ clock-mult = <1>;
+ clock-div = <2>;
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ pinctrl-0 = <&volume_up_n>;
+ pinctrl-names = "default";
+
+ key-volume-up {
+ label = "Volume Up";
+ linux,code = <KEY_VOLUMEUP>;
+ gpios = <&pm8550_gpios 6 GPIO_ACTIVE_LOW>;
+ debounce-interval = <15>;
+ linux,can-disable;
+ wakeup-source;
+ };
+ };
+
+ thermal-zones {
+ pm8550ve-d-thermal {
+ polling-delay-passive = <100>;
+
+ thermal-sensors = <&pm8550ve_d_temp_alarm>;
+
+ trips {
+ trip0 {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ trip1 {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "hot";
+ };
+ };
+ };
+
+ pm8550ve-f-thermal {
+ polling-delay-passive = <100>;
+
+ thermal-sensors = <&pm8550ve_f_temp_alarm>;
+
+ trips {
+ trip0 {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ trip1 {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "hot";
+ };
+ };
+ };
+
+ pm8550ve-g-thermal {
+ polling-delay-passive = <100>;
+
+ thermal-sensors = <&pm8550ve_g_temp_alarm>;
+
+ trips {
+ trip0 {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ trip1 {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "hot";
+ };
+ };
+ };
+
+ pm8550vs-j-thermal {
+ polling-delay-passive = <100>;
+
+ thermal-sensors = <&pm8550vs_j_temp_alarm>;
+
+ trips {
+ trip0 {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ trip1 {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "hot";
+ };
+ };
+ };
+ };
+
+ vph_pwr: vph-pwr-regulator {
+ compatible = "regulator-fixed";
+
+ regulator-name = "vph_pwr";
+ regulator-min-microvolt = <3700000>;
+ regulator-max-microvolt = <3700000>;
+
+ regulator-always-on;
+ regulator-boot-on;
+ };
+};
+
+&apps_rsc {
+ regulators-0 {
+ compatible = "qcom,pm8550-rpmh-regulators";
+
+ vdd-bob1-supply = <&vph_pwr>;
+ vdd-bob2-supply = <&vph_pwr>;
+ vdd-l2-l13-l14-supply = <&vreg_bob1>;
+ vdd-l3-supply = <&vreg_s7i_1p2>;
+ vdd-l5-l16-supply = <&vreg_bob1>;
+ vdd-l6-l7-supply = <&vreg_bob1>;
+ vdd-l8-l9-supply = <&vreg_bob1>;
+ vdd-l10-supply = <&vreg_s3g_1p8>;
+ vdd-l11-supply = <&vreg_s7i_1p2>;
+ vdd-l12-supply = <&vreg_s3g_1p8>;
+ vdd-l15-supply = <&vreg_s3g_1p8>;
+ vdd-l17-supply = <&vreg_bob2>;
+
+ qcom,pmic-id = "b";
+
+ vreg_bob1: bob1 {
+ regulator-name = "vreg_bob1";
+ regulator-min-microvolt = <3008000>;
+ regulator-max-microvolt = <4000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_bob2: bob2 {
+ regulator-name = "vreg_bob2";
+ regulator-min-microvolt = <2704000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l1b_1p8: ldo1 {
+ regulator-name = "vreg_l1b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2b_3p0: ldo2 {
+ regulator-name = "vreg_l2b_3p0";
+ regulator-min-microvolt = <3008000>;
+ regulator-max-microvolt = <3048000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l4b_1p8: ldo4 {
+ regulator-name = "vreg_l4b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l5b_3p1: ldo5 {
+ regulator-name = "vreg_l5b_3p1";
+ regulator-min-microvolt = <3100000>;
+ regulator-max-microvolt = <3148000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l6b_1p8: ldo6 {
+ regulator-name = "vreg_l6b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l7b_1p8: ldo7 {
+ regulator-name = "vreg_l7b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l8b_1p8: ldo8 {
+ regulator-name = "vreg_l8b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l9b_2p9: ldo9 {
+ regulator-name = "vreg_l9b_2p9";
+ regulator-min-microvolt = <2960000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l10b_1p8: ldo10 {
+ regulator-name = "vreg_l10b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l11b_1p0: ldo11 {
+ regulator-name = "vreg_l11b_1p0";
+ regulator-min-microvolt = <1064000>;
+ regulator-max-microvolt = <1292000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l12b_1p8: ldo12 {
+ regulator-name = "vreg_l12b_1p8";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l13b_3p0: ldo13 {
+ regulator-name = "vreg_l13b_3p0";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l14b_3p2: ldo14 {
+ regulator-name = "vreg_l14b_3p2";
+ regulator-min-microvolt = <3200000>;
+ regulator-max-microvolt = <3200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l15b_1p8: ldo15 {
+ regulator-name = "vreg_l15b_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l16b_2p8: ldo16 {
+ regulator-name = "vreg_l16b_2p8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l17b_2p5: ldo17 {
+ regulator-name = "vreg_l17b_2p5";
+ regulator-min-microvolt = <2504000>;
+ regulator-max-microvolt = <2504000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-1 {
+ compatible = "qcom,pm8550ve-rpmh-regulators";
+
+ vdd-l1-supply = <&vreg_s7i_1p2>;
+ vdd-l2-supply = <&vreg_s1d_0p97>;
+ vdd-l3-supply = <&vreg_s1d_0p97>;
+ vdd-s1-supply = <&vph_pwr>;
+ vdd-s3-supply = <&vph_pwr>;
+ vdd-s4-supply = <&vph_pwr>;
+
+ qcom,pmic-id = "d";
+
+ vreg_s1d_0p97: smps1 {
+ regulator-name = "vreg_s1d_0p97";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s3d_1p2: smps3 {
+ regulator-name = "vreg_s3d_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s4d_0p85: smps4 {
+ regulator-name = "vreg_s4d_0p85";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1036000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l1d_1p2: ldo1 {
+ regulator-name = "vreg_l1d_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2d_0p88: ldo2 {
+ regulator-name = "vreg_l2d_0p88";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <912000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3d_0p88: ldo3 {
+ regulator-name = "vreg_l3d_0p88";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <920000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-2 {
+ compatible = "qcom,pm8550ve-rpmh-regulators";
+
+ vdd-l1-supply = <&vreg_s1d_0p97>;
+ vdd-l2-supply = <&vreg_s7i_1p2>;
+ vdd-l3-supply = <&vreg_s3g_1p8>;
+ vdd-s5-supply = <&vph_pwr>;
+
+ qcom,pmic-id = "f";
+
+ vreg_s5f_0p5: smps5 {
+ regulator-name = "vreg_s5f_0p5";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l1f_0p88: ldo1 {
+ regulator-name = "vreg_l1f_0p88";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <920000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2f_1p2: ldo2 {
+ regulator-name = "vreg_l2f_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3f_1p8: ldo3 {
+ regulator-name = "vreg_l3f_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ };
+
+ regulators-3 {
+ compatible = "qcom,pm8550ve-rpmh-regulators";
+
+ vdd-l1-supply = <&vreg_s1d_0p97>;
+ vdd-l2-supply = <&vreg_s3g_1p8>;
+ vdd-l3-supply = <&vreg_s7i_1p2>;
+ vdd-s1-supply = <&vph_pwr>;
+ vdd-s3-supply = <&vph_pwr>;
+
+ qcom,pmic-id = "g";
+
+ vreg_s1g_0p5: smps1 {
+ regulator-name = "vreg_s1g_0p5";
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <700000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s3g_1p8: smps3 {
+ regulator-name = "vreg_s3g_1p8";
+ regulator-min-microvolt = <1856000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s4g_0p75: smps4 {
+ regulator-name = "vreg_s4g_0p75";
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <900000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l1g_0p91: ldo1 {
+ regulator-name = "vreg_l1g_0p91";
+ regulator-min-microvolt = <912000>;
+ regulator-max-microvolt = <936000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2g_1p8: ldo2 {
+ regulator-name = "vreg_l2g_1p8";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1860000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3g_1p2: ldo3 {
+ regulator-name = "vreg_l3g_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1256000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-4 {
+ compatible = "qcom,pm8550ve-rpmh-regulators";
+
+ vdd-l1-supply = <&vreg_s7i_1p2>;
+ vdd-l2-supply = <&vreg_s7i_1p2>;
+ vdd-l3-supply = <&vreg_s1d_0p97>;
+ vdd-s7-supply = <&vph_pwr>;
+ vdd-s8-supply = <&vph_pwr>;
+
+ qcom,pmic-id = "i";
+
+ vreg_s7i_1p2: smps7 {
+ regulator-name = "vreg_s7i_1p2";
+ regulator-min-microvolt = <1224000>;
+ regulator-max-microvolt = <1340000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s8i_0p9: smps8 {
+ regulator-name = "vreg_s8i_0p9";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <972000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l1i_1p2: ldo1 {
+ regulator-name = "vreg_l1i_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2i_1p2: ldo2 {
+ regulator-name = "vreg_l2i_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3i_0p88: ldo3 {
+ regulator-name = "vreg_l3i_0p88";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <912000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-5 {
+ compatible = "qcom,pm8550vs-rpmh-regulators";
+
+ vdd-l1-supply = <&vreg_s1d_0p97>;
+ vdd-l2-supply = <&vreg_s7i_1p2>;
+ vdd-s2-supply = <&vph_pwr>;
+ vdd-s3-supply = <&vph_pwr>;
+
+ qcom,pmic-id = "j";
+
+ vreg_s2j_1p1: smps2 {
+ regulator-name = "vreg_s2j_1p1";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s3j_1p1: smps3 {
+ regulator-name = "vreg_s3j_1p1";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+
+ vreg_l1j_0p91: ldo1 {
+ regulator-name = "vreg_l1j_0p91";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <920000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2j_1p2: ldo2 {
+ regulator-name = "vreg_l2j_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-6 {
+ compatible = "qcom,pm8010-rpmh-regulators";
+ qcom,pmic-id = "m";
+
+ vdd-l1-l2-supply = <&vreg_s7i_1p2>;
+ vdd-l3-l4-supply = <&vreg_s3g_1p8>;
+ vdd-l5-supply = <&vreg_s3g_1p8>;
+ vdd-l6-supply = <&vreg_bob1>;
+ vdd-l7-supply = <&vreg_bob1>;
+
+ vreg_l1m_1p1: ldo1 {
+ regulator-name = "vreg_l1m_1p1";
+ regulator-min-microvolt = <1104000>;
+ regulator-max-microvolt = <1104000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2m_1p056: ldo2 {
+ regulator-name = "vreg_l2m_1p056";
+ regulator-min-microvolt = <1056000>;
+ regulator-max-microvolt = <1056000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3m_2p8: ldo3 {
+ regulator-name = "vreg_l3m_2p8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l4m_2p8: ldo4 {
+ regulator-name = "vreg_l4m_2p8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l5m_1p8: ldo5 {
+ regulator-name = "vreg_l5m_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l6m_2p8: ldo6 {
+ regulator-name = "vreg_l6m_2p8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l7m_2p96: ldo7 {
+ regulator-name = "vreg_l7m_2p96";
+ regulator-min-microvolt = <2960000>;
+ regulator-max-microvolt = <2960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-7 {
+ compatible = "qcom,pm8010-rpmh-regulators";
+ qcom,pmic-id = "n";
+
+ vdd-l1-l2-supply = <&vreg_s7i_1p2>;
+ vdd-l3-l4-supply = <&vreg_s7i_1p2>;
+ vdd-l5-supply = <&vreg_bob2>;
+ vdd-l6-supply = <&vreg_bob2>;
+ vdd-l7-supply = <&vreg_bob1>;
+
+ vreg_l1n_1p1: ldo1 {
+ regulator-name = "vreg_l1n_1p1";
+ regulator-min-microvolt = <1104000>;
+ regulator-max-microvolt = <1104000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2n_1p1: ldo2 {
+ regulator-name = "vreg_l2n_1p1";
+ regulator-min-microvolt = <1104000>;
+ regulator-max-microvolt = <1104000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3n_1p8: ldo3 {
+ regulator-name = "vreg_l3n_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l4n_1p8: ldo4 {
+ regulator-name = "vreg_l4n_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l5n_2p8: ldo5 {
+ regulator-name = "vreg_l5n_2p8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l6n_2p8: ldo6 {
+ regulator-name = "vreg_l6n_2p8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l7n_3p3: ldo7 {
+ regulator-name = "vreg_l7n_3p3";
+ regulator-min-microvolt = <3304000>;
+ regulator-max-microvolt = <3304000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+};
+
+&pm8550_flash {
+ status = "okay";
+
+ led-0 {
+ function = LED_FUNCTION_FLASH;
+ color = <LED_COLOR_ID_YELLOW>;
+ led-sources = <1>, <4>;
+ led-max-microamp = <500000>;
+ flash-max-microamp = <2000000>;
+ flash-max-timeout-us = <1280000>;
+ function-enumerator = <0>;
+ };
+
+ led-1 {
+ function = LED_FUNCTION_FLASH;
+ color = <LED_COLOR_ID_WHITE>;
+ led-sources = <2>, <3>;
+ led-max-microamp = <500000>;
+ flash-max-microamp = <2000000>;
+ flash-max-timeout-us = <1280000>;
+ function-enumerator = <1>;
+ };
+};
+
+&pm8550_gpios {
+ volume_up_n: volume-up-n-state {
+ pins = "gpio6";
+ function = "normal";
+ bias-pull-up;
+ input-enable;
+ power-source = <1>;
+ };
+};
+
+&pm8550_pwm {
+ status = "okay";
+
+ multi-led {
+ color = <LED_COLOR_ID_RGB>;
+ function = LED_FUNCTION_STATUS;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ led@1 {
+ reg = <1>;
+ color = <LED_COLOR_ID_RED>;
+ };
+
+ led@2 {
+ reg = <2>;
+ color = <LED_COLOR_ID_GREEN>;
+ };
+
+ led@3 {
+ reg = <3>;
+ color = <LED_COLOR_ID_BLUE>;
+ };
+ };
+};
+
+&pon_pwrkey {
+ status = "okay";
+};
+
+&pon_resin {
+ linux,code = <KEY_VOLUMEDOWN>;
+
+ status = "okay";
+};
+
+&pmih0108_eusb2_repeater {
+ status = "okay";
+
+ vdd18-supply = <&vreg_l15b_1p8>;
+ vdd3-supply = <&vreg_l5b_3p1>;
+};
+
+&qupv3_1 {
+ status = "okay";
+};
+
+&spmi_bus {
+ pm8550ve_d: pmic@3 {
+ compatible = "qcom,pm8550ve", "qcom,spmi-pmic";
+ reg = <0x3 SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pm8550ve_d_temp_alarm: temp-alarm@a00 {
+ compatible = "qcom,spmi-temp-alarm";
+ reg = <0xa00>;
+ interrupts = <0x3 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
+ #thermal-sensor-cells = <0>;
+ };
+
+ pm8550ve_d_gpios: gpio@8800 {
+ compatible = "qcom,pm8550ve-gpio", "qcom,spmi-gpio";
+ reg = <0x8800>;
+ gpio-controller;
+ gpio-ranges = <&pm8550ve_d_gpios 0 0 8>;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ pm8550ve_f: pmic@5 {
+ compatible = "qcom,pm8550ve", "qcom,spmi-pmic";
+ reg = <0x5 SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pm8550ve_f_temp_alarm: temp-alarm@a00 {
+ compatible = "qcom,spmi-temp-alarm";
+ reg = <0xa00>;
+ interrupts = <0x5 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
+ #thermal-sensor-cells = <0>;
+ };
+
+ pm8550ve_f_gpios: gpio@8800 {
+ compatible = "qcom,pm8550ve-gpio", "qcom,spmi-gpio";
+ reg = <0x8800>;
+ gpio-controller;
+ gpio-ranges = <&pm8550ve_f_gpios 0 0 6>;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ pm8550ve_g: pmic@6 {
+ compatible = "qcom,pm8550ve", "qcom,spmi-pmic";
+ reg = <0x6 SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pm8550ve_g_temp_alarm: temp-alarm@a00 {
+ compatible = "qcom,spmi-temp-alarm";
+ reg = <0xa00>;
+ interrupts = <0x6 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
+ #thermal-sensor-cells = <0>;
+ };
+
+ pm8550ve_g_gpios: gpio@8800 {
+ compatible = "qcom,pm8550ve-gpio", "qcom,spmi-gpio";
+ reg = <0x8800>;
+ gpio-controller;
+ gpio-ranges = <&pm8550ve_g_gpios 0 0 8>;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ pm8550vs_j: pmic@9 {
+ compatible = "qcom,pm8550vs", "qcom,spmi-pmic";
+ reg = <0x9 SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pm8550vs_j_temp_alarm: temp-alarm@a00 {
+ compatible = "qcom,spmi-temp-alarm";
+ reg = <0xa00>;
+ interrupts = <0x9 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
+ #thermal-sensor-cells = <0>;
+ };
+
+ pm8550vs_j_gpios: gpio@8800 {
+ compatible = "qcom,pm8550vs-gpio", "qcom,spmi-gpio";
+ reg = <0x8800>;
+ gpio-controller;
+ gpio-ranges = <&pm8550vs_j_gpios 0 0 6>;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+};
+
+&uart7 {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi
new file mode 100644
index 000000000000..98ab82caa007
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi
@@ -0,0 +1,2903 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/clock/qcom,sm8750-gcc.h>
+#include <dt-bindings/clock/qcom,sm8750-tcsr.h>
+#include <dt-bindings/dma/qcom-gpi.h>
+#include <dt-bindings/interconnect/qcom,icc.h>
+#include <dt-bindings/interconnect/qcom,sm8750-rpmh.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/power/qcom,rpmhpd.h>
+#include <dt-bindings/power/qcom-rpmpd.h>
+#include <dt-bindings/soc/qcom,rpmh-rsc.h>
+
+/ {
+ interrupt-parent = <&intc>;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ chosen { };
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ CPU0: cpu@0 {
+ device_type = "cpu";
+ compatible = "qcom,oryon";
+ reg = <0x0 0x0>;
+ enable-method = "psci";
+ next-level-cache = <&L2_0>;
+ power-domains = <&CPU_PD0>;
+ power-domain-names = "psci";
+ cpu-idle-states = <&CLUSTER0_C4>;
+
+ L2_0: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
+ };
+ };
+
+ CPU1: cpu@100 {
+ device_type = "cpu";
+ compatible = "qcom,oryon";
+ reg = <0x0 0x100>;
+ enable-method = "psci";
+ next-level-cache = <&L2_0>;
+ power-domains = <&CPU_PD1>;
+ power-domain-names = "psci";
+ cpu-idle-states = <&CLUSTER0_C4>;
+ };
+
+ CPU2: cpu@200 {
+ device_type = "cpu";
+ compatible = "qcom,oryon";
+ reg = <0x0 0x200>;
+ enable-method = "psci";
+ next-level-cache = <&L2_0>;
+ power-domains = <&CPU_PD2>;
+ power-domain-names = "psci";
+ cpu-idle-states = <&CLUSTER0_C4>;
+ };
+
+ CPU3: cpu@300 {
+ device_type = "cpu";
+ compatible = "qcom,oryon";
+ reg = <0x0 0x300>;
+ enable-method = "psci";
+ next-level-cache = <&L2_0>;
+ power-domains = <&CPU_PD3>;
+ power-domain-names = "psci";
+ cpu-idle-states = <&CLUSTER0_C4>;
+ };
+
+ CPU4: cpu@400 {
+ device_type = "cpu";
+ compatible = "qcom,oryon";
+ reg = <0x0 0x400>;
+ enable-method = "psci";
+ next-level-cache = <&L2_0>;
+ power-domains = <&CPU_PD4>;
+ power-domain-names = "psci";
+ cpu-idle-states = <&CLUSTER0_C4>;
+ };
+
+ CPU5: cpu@500 {
+ device_type = "cpu";
+ compatible = "qcom,oryon";
+ reg = <0x0 0x500>;
+ enable-method = "psci";
+ next-level-cache = <&L2_0>;
+ power-domains = <&CPU_PD5>;
+ power-domain-names = "psci";
+ cpu-idle-states = <&CLUSTER0_C4>;
+ };
+
+ CPU6: cpu@10000 {
+ device_type = "cpu";
+ compatible = "qcom,oryon";
+ reg = <0x0 0x10000>;
+ enable-method = "psci";
+ next-level-cache = <&L2_1>;
+ power-domains = <&CPU_PD6>;
+ power-domain-names = "psci";
+ cpu-idle-states = <&CLUSTER1_C4>;
+
+ L2_1: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
+ };
+ };
+
+ CPU7: cpu@10100 {
+ device_type = "cpu";
+ compatible = "qcom,oryon";
+ reg = <0x0 0x10100>;
+ enable-method = "psci";
+ next-level-cache = <&L2_1>;
+ power-domains = <&CPU_PD7>;
+ power-domain-names = "psci";
+ cpu-idle-states = <&CLUSTER1_C4>;
+ };
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&CPU0>;
+ };
+
+ core1 {
+ cpu = <&CPU1>;
+ };
+
+ core2 {
+ cpu = <&CPU2>;
+ };
+
+ core3 {
+ cpu = <&CPU3>;
+ };
+
+ core4 {
+ cpu = <&CPU4>;
+ };
+
+ core5 {
+ cpu = <&CPU5>;
+ };
+ };
+
+ cluster1 {
+ core0 {
+ cpu = <&CPU6>;
+ };
+
+ core1 {
+ cpu = <&CPU7>;
+ };
+ };
+ };
+
+ idle-states {
+ entry-method = "psci";
+
+ CLUSTER0_C4: cpu-sleep-0 {
+ compatible = "arm,idle-state";
+ idle-state-name = "ret";
+ arm,psci-suspend-param = <0x00000004>;
+ entry-latency-us = <93>;
+ exit-latency-us = <129>;
+ min-residency-us = <560>;
+ };
+
+ CLUSTER1_C4: cpu-sleep-1 {
+ compatible = "arm,idle-state";
+ idle-state-name = "ret";
+ arm,psci-suspend-param = <0x00000004>;
+ entry-latency-us = <172>;
+ exit-latency-us = <130>;
+ min-residency-us = <686>;
+ };
+
+ };
+
+ domain-idle-states {
+ CLUSTER_CL5: cluster-sleep-0 {
+ compatible = "arm,idle-state";
+ idle-state-name = "ret-pll-off";
+ arm,psci-suspend-param = <0x01000054>;
+ entry-latency-us = <2150>;
+ exit-latency-us = <1983>;
+ min-residency-us = <9144>;
+ };
+ };
+ };
+
+ firmware {
+ scm: scm {
+ compatible = "qcom,scm-sm8750", "qcom,scm";
+ interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ };
+ };
+
+ clk_virt: interconnect-0 {
+ compatible = "qcom,sm8750-clk-virt";
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ mc_virt: interconnect-1 {
+ compatible = "qcom,sm8750-mc-virt";
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ memory@a0000000 {
+ device_type = "memory";
+ /* We expect the bootloader to fill in the size */
+ reg = <0x0 0xa0000000 0x0 0x0>;
+ };
+
+ pmu {
+ compatible = "arm,armv8-pmuv3";
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+
+ CPU_PD0: power-domain-cpu0 {
+ #power-domain-cells = <0>;
+ power-domains = <&CLUSTER_PD0>;
+ };
+
+ CPU_PD1: power-domain-cpu1 {
+ #power-domain-cells = <0>;
+ power-domains = <&CLUSTER_PD0>;
+ };
+
+ CPU_PD2: power-domain-cpu2 {
+ #power-domain-cells = <0>;
+ power-domains = <&CLUSTER_PD0>;
+ };
+
+ CPU_PD3: power-domain-cpu3 {
+ #power-domain-cells = <0>;
+ power-domains = <&CLUSTER_PD0>;
+ };
+
+ CPU_PD4: power-domain-cpu4 {
+ #power-domain-cells = <0>;
+ power-domains = <&CLUSTER_PD0>;
+ };
+
+ CPU_PD5: power-domain-cpu5 {
+ #power-domain-cells = <0>;
+ power-domains = <&CLUSTER_PD0>;
+ };
+
+ CPU_PD6: power-domain-cpu6 {
+ #power-domain-cells = <0>;
+ power-domains = <&CLUSTER_PD1>;
+ };
+
+ CPU_PD7: power-domain-cpu7 {
+ #power-domain-cells = <0>;
+ power-domains = <&CLUSTER_PD1>;
+ };
+
+ CLUSTER_PD0: power-domain-cpu-cluster0 {
+ #power-domain-cells = <0>;
+ domain-idle-states = <&CLUSTER_CL5>;
+ };
+
+ CLUSTER_PD1: power-domain-cpu-cluster1 {
+ #power-domain-cells = <0>;
+ domain-idle-states = <&CLUSTER_CL5>;
+ };
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ gunyah_hyp_mem: gunyah-hyp@80000000 {
+ reg = <0x0 0x80000000 0x0 0xe00000>;
+ no-map;
+ };
+
+ cpusys_vm_mem: cpusys-vm-mem@80e00000 {
+ reg = <0x0 0x80e00000 0x0 0x40000>;
+ no-map;
+ };
+
+ cpucp_mem: cpucp@81200000 {
+ reg = <0x0 0x81200000 0x0 0x200000>;
+ no-map;
+ };
+
+ xbl_dtlog_mem: xbl-dtlog@81a00000 {
+ reg = <0x0 0x81a00000 0x0 0x40000>;
+ no-map;
+ };
+
+ aop_image_mem: aop-image@81c00000 {
+ reg = <0x0 0x81c00000 0x0 0x60000>;
+ no-map;
+ };
+
+ aop_cmd_db_mem: aop-cmd-db@81c60000 {
+ compatible = "qcom,cmd-db";
+ reg = <0x0 0x81c60000 0x0 0x20000>;
+ no-map;
+ };
+
+ /* Merged aop_config, tme_crash_dump, tme_log and uefi_log regions */
+ aop_tme_uefi_merged_mem: aop-tme-uefi-merged@81c80000 {
+ reg = <0x0 0x81c80000 0x0 0x74000>;
+ no-map;
+ };
+
+ /* Secdata region can be reused by apps */
+
+ smem_mem: smem@81d00000 {
+ compatible = "qcom,smem";
+ reg = <0x0 0x81d00000 0x0 0x200000>;
+ hwlocks = <&tcsr_mutex 3>;
+ no-map;
+ };
+
+ pdp_ns_shared_mem: pdp-ns-shared@81f00000 {
+ reg = <0x0 0x81f00000 0x0 0x100000>;
+ no-map;
+ };
+
+ cpucp_scandump_mem: cpucp-scandump@82000000 {
+ reg = <0x0 0x82000000 0x0 0x380000>;
+ no-map;
+ };
+
+ adsp_mhi_mem: adsp-mhi@82380000 {
+ reg = <0x0 0x82380000 0x0 0x20000>;
+ no-map;
+ };
+
+ soccp_sdi_mem: soccp-sdi@823a0000 {
+ reg = <0x0 0x823a0000 0x0 0x40000>;
+ no-map;
+ };
+
+ pmic_minii_dump_mem: pmic-minii-dump@823e0000 {
+ reg = <0x0 0x823e0000 0x0 0x80000>;
+ no-map;
+ };
+
+ pvmfw_mem: pvmfw@824a0000 {
+ reg = <0x0 0x824a0000 0x0 0x100000>;
+ no-map;
+ };
+
+ global_sync_mem: global-sync@82600000 {
+ reg = <0x0 0x82600000 0x0 0x100000>;
+ no-map;
+ };
+
+ tz_stat_mem: tz-stat@82700000 {
+ reg = <0x0 0x82700000 0x0 0x100000>;
+ no-map;
+ };
+
+ qdss_mem: qdss@82800000 {
+ reg = <0x0 0x82800000 0x0 0x2000000>;
+ no-map;
+ };
+
+ dsm_partition_1_mem: dsm-partition-1@84a00000 {
+ reg = <0x0 0x84a00000 0x0 0x4900000>;
+ no-map;
+ };
+
+ dsm_partition_2_mem: dsm-partition-2@89300000 {
+ reg = <0x0 0x89300000 0x0 0xa80000>;
+ no-map;
+ };
+
+ mpss_mem: mpss@8ba00000 {
+ reg = <0x0 0x8ba00000 0x0 0xf600000>;
+ no-map;
+ };
+
+ q6_mpss_dtb_mem: q6-mpss-dtb@9b000000 {
+ reg = <0x0 0x9b000000 0x0 0x80000>;
+ no-map;
+ };
+
+ ipa_fw_mem: ipa-fw@9b080000 {
+ reg = <0x0 0x9b080000 0x0 0x10000>;
+ no-map;
+ };
+
+ ipa_gsi_mem: ipa-gsi@9b090000 {
+ reg = <0x0 0x9b090000 0x0 0xa000>;
+ no-map;
+ };
+
+ gpu_micro_code_mem: gpu-micro-code@9b09a000 {
+ reg = <0x0 0x9b09a000 0x0 0x2000>;
+ no-map;
+ };
+
+ spss_region_mem: spss@9b0a0000 {
+ reg = <0x0 0x9b0a0000 0x0 0x1e0000>;
+ no-map;
+ };
+
+ /* First part of the "SPU secure shared memory" region */
+ spu_tz_shared_mem: spu-tz-shared@9b280000 {
+ reg = <0x0 0x9b280000 0x0 0x40000>;
+ no-map;
+ };
+
+ /* Second part of the "SPU secure shared memory" region */
+ spu_modem_shared_mem: spu-modem-shared@9b2c0000 {
+ reg = <0x0 0x9b2c0000 0x0 0x40000>;
+ no-map;
+ };
+
+ camera_mem: camera@9b300000 {
+ reg = <0x0 0x9b300000 0x0 0x800000>;
+ no-map;
+ };
+
+ camera_2_mem: camera-2@9bb00000 {
+ reg = <0x0 0x9bb00000 0x0 0x800000>;
+ no-map;
+ };
+
+ video_mem: video@9c300000 {
+ reg = <0x0 0x9c300000 0x0 0x800000>;
+ no-map;
+ };
+
+ cvp_mem: cvp@9cb00000 {
+ reg = <0x0 0x9cb00000 0x0 0x700000>;
+ no-map;
+ };
+
+ cdsp_mem: cdsp@9d200000 {
+ reg = <0x0 0x9d200000 0x0 0x1900000>;
+ no-map;
+ };
+
+ q6_cdsp_dtb_mem: q6-cdsp-dtb@9eb00000 {
+ reg = <0x0 0x9eb00000 0x0 0x80000>;
+ no-map;
+ };
+
+ soccp_mem: soccp@9ec00000 {
+ reg = <0x0 0x9ec00000 0x0 0x180000>;
+ no-map;
+ };
+
+ q6_adsp_dtb_mem: q6-adsp-dtb@9ed80000 {
+ reg = <0x0 0x9ed80000 0x0 0x80000>;
+ no-map;
+ };
+
+ adspslpi_mem: adspslpi@9ee00000 {
+ reg = <0x0 0x9ee00000 0x0 0x3a80000>;
+ no-map;
+ };
+
+ xbl_ramdump_mem: xbl-ramdump@b8000000 {
+ reg = <0x0 0xb8000000 0x0 0x1c0000>;
+ no-map;
+ };
+
+ hwfence_shbuf: hwfence-shbuf@d4e23000 {
+ no-map;
+ reg = <0x0 0xd4e23000 0x0 0x2dd000>;
+ };
+
+ /* Merged tz_reserved, xbl_sc, and qtee regions */
+ tz_merged_mem: tz-merged@d8000000 {
+ reg = <0x0 0xd8000000 0x0 0x600000>;
+ no-map;
+ };
+
+ trust_ui_vm_mem: trust-ui-vm@f3800000 {
+ reg = <0x0 0xf3800000 0x0 0x4400000>;
+ no-map;
+ };
+
+ oem_vm_mem: oem-vm@f7c00000 {
+ reg = <0x0 0xf7c00000 0x0 0x4c00000>;
+ no-map;
+ };
+
+ llcc_lpi_mem: llcc-lpi@ff800000 {
+ reg = <0x0 0xff800000 0x0 0x800000>;
+ no-map;
+ };
+ };
+
+ soc: soc@0 {
+ compatible = "simple-bus";
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ dma-ranges = <0 0 0 0 0x10 0>;
+ ranges = <0 0 0 0 0x10 0>;
+
+ gcc: clock-controller@100000 {
+ compatible = "qcom,sm8750-gcc";
+ reg = <0x0 0x00100000 0x0 0x1f4200>;
+
+ clocks = <&bi_tcxo>,
+ <&sleep_clk>,
+ <0>,
+ <0>,
+ <0>,
+ <0>,
+ <0>,
+ <0>,
+ <0>,
+ <0>;
+
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
+ gpi_dma2: dma-controller@800000 {
+ compatible = "qcom,sm8750-gpi-dma", "qcom,sm6350-gpi-dma";
+ reg = <0x0 0x00800000 0x0 0x60000>;
+
+ interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>;
+
+ dma-channels = <12>;
+ dma-channel-mask = <0x1e>;
+ #dma-cells = <3>;
+
+ iommus = <&apps_smmu 0x436 0x0>;
+
+ status = "disabled";
+ };
+
+ qupv3_2: geniqup@8c0000 {
+ compatible = "qcom,geni-se-qup";
+ reg = <0x0 0x008c0000 0x0 0x2000>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
+ <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
+ clock-names = "m-ahb",
+ "s-ahb";
+
+ iommus = <&apps_smmu 0x423 0x0>;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ status = "disabled";
+
+ i2c8: i2c@880000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x00880000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
+ <&gpi_dma2 1 0 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_i2c8_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ spi8: spi@880000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0x00880000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
+ <&gpi_dma2 1 0 QCOM_GPI_SPI>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ i2c9: i2c@884000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x00884000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
+ <&gpi_dma2 1 1 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_i2c9_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ spi9: spi@884000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0x00884000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
+ <&gpi_dma2 1 1 QCOM_GPI_SPI>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ i2c10: i2c@888000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x00888000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
+ <&gpi_dma2 1 2 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_i2c10_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ spi10: spi@888000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0x00888000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
+ <&gpi_dma2 1 2 QCOM_GPI_SPI>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ i2c11: i2c@88c000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x0088c000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
+ <&gpi_dma2 1 3 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_i2c11_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ spi11: spi@88c000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0x0088c000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>,
+ <&gpi_dma2 1 3 QCOM_GPI_SPI>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ i2c12: i2c@890000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x00890000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
+ <&gpi_dma2 1 4 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_i2c12_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ spi12: spi@890000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0x00890000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>,
+ <&gpi_dma2 1 4 QCOM_GPI_SPI>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ i2c13: i2c@894000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x00894000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
+ <&gpi_dma2 1 5 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_i2c13_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ spi13: spi@894000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0x00894000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
+ <&gpi_dma2 1 5 QCOM_GPI_SPI>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ uart14: serial@898000 {
+ compatible = "qcom,geni-uart";
+ reg = <0x0 0x00898000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ pinctrl-0 = <&qup_uart14_default>;
+ pinctrl-names = "default";
+
+ status = "disabled";
+ };
+
+ i2c15: i2c@89c000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x0089c000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma2 0 7 QCOM_GPI_I2C>,
+ <&gpi_dma2 1 7 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_i2c15_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ spi15: spi@89c000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0x0089c000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma2 0 7 QCOM_GPI_SPI>,
+ <&gpi_dma2 1 7 QCOM_GPI_SPI>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+ };
+
+ i2c_master_hub_0: geniqup@9c0000 {
+ compatible = "qcom,geni-se-i2c-master-hub";
+ reg = <0x0 0x009c0000 0x0 0x2000>;
+
+ clocks = <&gcc GCC_QUPV3_I2C_S_AHB_CLK>;
+ clock-names = "s-ahb";
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ status = "disabled";
+
+ i2c_hub_0: i2c@980000 {
+ compatible = "qcom,geni-i2c-master-hub";
+ reg = <0x0 0x00980000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_I2C_S0_CLK>,
+ <&gcc GCC_QUPV3_I2C_CORE_CLK>;
+ clock-names = "se",
+ "core";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ pinctrl-0 = <&hub_i2c0_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ i2c_hub_1: i2c@984000 {
+ compatible = "qcom,geni-i2c-master-hub";
+ reg = <0x0 0x00984000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_I2C_S1_CLK>,
+ <&gcc GCC_QUPV3_I2C_CORE_CLK>;
+ clock-names = "se",
+ "core";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ pinctrl-0 = <&hub_i2c1_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ i2c_hub_2: i2c@988000 {
+ compatible = "qcom,geni-i2c-master-hub";
+ reg = <0x0 0x00988000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_I2C_S2_CLK>,
+ <&gcc GCC_QUPV3_I2C_CORE_CLK>;
+ clock-names = "se",
+ "core";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ pinctrl-0 = <&hub_i2c2_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ i2c_hub_3: i2c@98c000 {
+ compatible = "qcom,geni-i2c-master-hub";
+ reg = <0x0 0x0098c000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_I2C_S3_CLK>,
+ <&gcc GCC_QUPV3_I2C_CORE_CLK>;
+ clock-names = "se",
+ "core";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ pinctrl-0 = <&hub_i2c3_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ i2c_hub_4: i2c@990000 {
+ compatible = "qcom,geni-i2c-master-hub";
+ reg = <0x0 0x00990000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_I2C_S4_CLK>,
+ <&gcc GCC_QUPV3_I2C_CORE_CLK>;
+ clock-names = "se",
+ "core";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ pinctrl-0 = <&hub_i2c4_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ i2c_hub_5: i2c@994000 {
+ compatible = "qcom,geni-i2c-master-hub";
+ reg = <0x0 0x00994000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_I2C_S5_CLK>,
+ <&gcc GCC_QUPV3_I2C_CORE_CLK>;
+ clock-names = "se",
+ "core";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ pinctrl-0 = <&hub_i2c5_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ i2c_hub_6: i2c@998000 {
+ compatible = "qcom,geni-i2c-master-hub";
+ reg = <0x0 0x00998000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_I2C_S6_CLK>,
+ <&gcc GCC_QUPV3_I2C_CORE_CLK>;
+ clock-names = "se",
+ "core";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ pinctrl-0 = <&hub_i2c6_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ i2c_hub_7: i2c@99c000 {
+ compatible = "qcom,geni-i2c-master-hub";
+ reg = <0x0 0x0099c000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_I2C_S7_CLK>,
+ <&gcc GCC_QUPV3_I2C_CORE_CLK>;
+ clock-names = "se",
+ "core";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ pinctrl-0 = <&hub_i2c7_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ i2c_hub_8: i2c@9a0000 {
+ compatible = "qcom,geni-i2c-master-hub";
+ reg = <0x0 0x009a0000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_I2C_S8_CLK>,
+ <&gcc GCC_QUPV3_I2C_CORE_CLK>;
+ clock-names = "se",
+ "core";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ pinctrl-0 = <&hub_i2c8_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ i2c_hub_9: i2c@9a4000 {
+ compatible = "qcom,geni-i2c-master-hub";
+ reg = <0x0 0x009a4000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_I2C_S9_CLK>,
+ <&gcc GCC_QUPV3_I2C_CORE_CLK>;
+ clock-names = "se",
+ "core";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ pinctrl-0 = <&hub_i2c9_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+ };
+
+ gpi_dma1: dma-controller@a00000 {
+ compatible = "qcom,sm8750-gpi-dma", "qcom,sm6350-gpi-dma";
+ reg = <0x0 0x00a00000 0x0 0x60000>;
+
+ interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
+
+ dma-channels = <12>;
+ dma-channel-mask = <0x1e>;
+ #dma-cells = <3>;
+
+ iommus = <&apps_smmu 0xb6 0x0>;
+
+ status = "disabled";
+ };
+
+ qupv3_1: geniqup@ac0000 {
+ compatible = "qcom,geni-se-qup";
+ reg = <0x0 0x00ac0000 0x0 0x2000>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
+ <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
+ clock-names = "m-ahb",
+ "s-ahb";
+
+ iommus = <&apps_smmu 0xa3 0x0>;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ status = "disabled";
+
+ i2c0: i2c@a80000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x00a80000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
+ <&gpi_dma1 1 0 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_i2c0_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ spi0: spi@a80000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0x00a80000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
+ <&gpi_dma1 1 0 QCOM_GPI_SPI>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ i2c1: i2c@a84000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x00a84000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
+ <&gpi_dma1 1 1 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_i2c1_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ spi1: spi@a84000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0x00a84000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
+ <&gpi_dma1 1 1 QCOM_GPI_SPI>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ i2c2: i2c@a88000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x00a88000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
+ <&gpi_dma1 1 2 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_i2c2_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ spi2: spi@a88000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0x00a88000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
+ <&gpi_dma1 1 2 QCOM_GPI_SPI>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ i2c3: i2c@a8c000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x00a8c000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
+ <&gpi_dma1 1 3 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_i2c3_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ spi3: spi@a8c000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0x00a8c000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
+ <&gpi_dma1 1 3 QCOM_GPI_SPI>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ i2c4: i2c@a90000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x00a90000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
+ <&gpi_dma1 1 4 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_i2c4_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ spi4: spi@a90000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0x00a90000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
+ <&gpi_dma1 1 4 QCOM_GPI_SPI>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ i2c5: i2c@a94000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x00a94000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
+ <&gpi_dma1 1 5 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_i2c5_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ spi5: spi@a94000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0x00a94000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
+ <&gpi_dma1 1 5 QCOM_GPI_SPI>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ i2c6: i2c@a98000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x00a98000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
+ <&gpi_dma1 1 6 QCOM_GPI_I2C>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_i2c6_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ spi6: spi@a98000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0x00a98000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
+ <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>,
+ <&gpi_dma1 1 6 QCOM_GPI_SPI>;
+ dma-names = "tx",
+ "rx";
+
+ pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ uart7: serial@a9c000 {
+ compatible = "qcom,geni-debug-uart";
+ reg = <0x0 0x00a9c000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+
+ pinctrl-0 = <&qup_uart7_default>;
+ pinctrl-names = "default";
+
+ status = "disabled";
+ };
+ };
+
+
+ cnoc_main: interconnect@1500000 {
+ compatible = "qcom,sm8750-cnoc-main";
+ reg = <0x0 0x1500000 0x0 0x16080>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ #interconnect-cells = <2>;
+ };
+
+ config_noc: interconnect@1600000 {
+ compatible = "qcom,sm8750-cnoc-cfg";
+ reg = <0x0 0x1600000 0x0 0x6200>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ #interconnect-cells = <2>;
+ };
+
+ system_noc: interconnect@1680000 {
+ compatible = "qcom,sm8750-system-noc";
+ reg = <0x0 0x1680000 0x0 0x1d080>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ #interconnect-cells = <2>;
+ };
+
+ pcie_noc: interconnect@16c0000 {
+ compatible = "qcom,sm8750-pcie-anoc";
+ reg = <0x0 0x16c0000 0x0 0x11400>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ #interconnect-cells = <2>;
+ clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
+ <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>;
+
+ };
+
+ aggre1_noc: interconnect@16e0000 {
+ compatible = "qcom,sm8750-aggre1-noc";
+ reg = <0x0 0x16e0000 0x0 0x16400>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ #interconnect-cells = <2>;
+ clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
+ <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>;
+
+ };
+
+ aggre2_noc: interconnect@1700000 {
+ compatible = "qcom,sm8750-aggre2-noc";
+ reg = <0x0 0x1700000 0x0 0x1f400>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ #interconnect-cells = <2>;
+ clocks = <&rpmhcc RPMH_IPA_CLK>;
+ };
+
+ mmss_noc: interconnect@1780000 {
+ compatible = "qcom,sm8750-mmss-noc";
+ reg = <0x0 0x1780000 0x0 0x5b800>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ #interconnect-cells = <2>;
+ };
+
+ tcsr_mutex: hwlock@1f40000 {
+ compatible = "qcom,tcsr-mutex";
+ reg = <0x0 0x01f40000 0x0 0x20000>;
+ #hwlock-cells = <1>;
+ };
+
+ lpass_ag_noc: interconnect@7e40000 {
+ compatible = "qcom,sm8750-lpass-ag-noc";
+ reg = <0x0 0x7e40000 0x0 0xe080>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ #interconnect-cells = <2>;
+ };
+
+ lpass_lpiaon_noc: interconnect@7400000 {
+ compatible = "qcom,sm8750-lpass-lpiaon-noc";
+ reg = <0x0 0x7400000 0x0 0x19080>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ #interconnect-cells = <2>;
+ };
+
+ lpass_lpicx_noc: interconnect@7420000 {
+ compatible = "qcom,sm8750-lpass-lpicx-noc";
+ reg = <0x0 0x7420000 0x0 0x44080>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ #interconnect-cells = <2>;
+ };
+
+ pdc: interrupt-controller@b220000 {
+ compatible = "qcom,sm8750-pdc", "qcom,pdc";
+ reg = <0x0 0x0b220000 0x0 0x10000>, <0x0 0x164400f0 0x0 0x64>;
+
+ qcom,pdc-ranges = <0 745 51>, <51 527 47>,
+ <98 609 32>, <130 717 12>,
+ <142 251 5>, <147 796 16>;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&intc>;
+ interrupt-controller;
+ };
+
+ spmi_bus: spmi@c400000 {
+ compatible = "qcom,spmi-pmic-arb";
+ reg = <0x0 0xc400000 0x0 0x3000>,
+ <0x0 0xc500000 0x0 0x400000>,
+ <0x0 0xc440000 0x0 0x80000>,
+ <0x0 0xc4c0000 0x0 0x10000>,
+ <0x0 0xc42d000 0x0 0x4000>;
+ reg-names = "core",
+ "chnls",
+ "obsrvr",
+ "intr",
+ "cnfg";
+
+ interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "periph_irq";
+
+ qcom,ee = <0>;
+ qcom,channel = <0>;
+ qcom,bus-id = <0>;
+
+ interrupt-controller;
+ #interrupt-cells = <4>;
+
+ #address-cells = <2>;
+ #size-cells = <0>;
+ };
+
+ tlmm: pinctrl@f100000 {
+ compatible = "qcom,sm8750-tlmm";
+ reg = <0x0 0x0f100000 0x0 0x102000>;
+
+ interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ gpio-ranges = <&tlmm 0 0 220>;
+ wakeup-parent = <&pdc>;
+
+ hub_i2c0_data_clk: hub-i2c0-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio64", "gpio65";
+ function = "i2chub0_se0";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ hub_i2c1_data_clk: hub-i2c1-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio66", "gpio67";
+ function = "i2chub0_se1";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ hub_i2c2_data_clk: hub-i2c2-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio68", "gpio69";
+ function = "i2chub0_se2";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ hub_i2c3_data_clk: hub-i2c3-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio70", "gpio71";
+ function = "i2chub0_se3";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ hub_i2c4_data_clk: hub-i2c4-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio72", "gpio73";
+ function = "i2chub0_se4";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ hub_i2c5_data_clk: hub-i2c5-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio74", "gpio75";
+ function = "i2chub0_se5";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ hub_i2c6_data_clk: hub-i2c6-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio76", "gpio77";
+ function = "i2chub0_se6";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ hub_i2c7_data_clk: hub-i2c7-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio82", "gpio83";
+ function = "i2chub0_se7";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ hub_i2c8_data_clk: hub-i2c8-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio206", "gpio207";
+ function = "i2chub0_se8";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ hub_i2c9_data_clk: hub-i2c9-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio80", "gpio81";
+ function = "i2chub0_se9";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ pcie0_default_state: pcie0-default-state {
+ perst-pins {
+ pins = "gpio102";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ clkreq-pins {
+ pins = "gpio103";
+ function = "pcie0_clk_req_n";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ wake-pins {
+ pins = "gpio104";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ qup_i2c0_data_clk: qup-i2c0-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio32", "gpio33";
+ function = "qup1_se0";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_i2c1_data_clk: qup-i2c1-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio36", "gpio37";
+ function = "qup1_se1";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_i2c2_data_clk: qup-i2c2-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio40", "gpio41";
+ function = "qup1_se2";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_i2c3_data_clk: qup-i2c3-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio44", "gpio45";
+ function = "qup1_se3";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_i2c4_data_clk: qup-i2c4-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio48", "gpio49";
+ function = "qup1_se4";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_i2c5_data_clk: qup-i2c5-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio52", "gpio53";
+ function = "qup1_se5";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_i2c6_data_clk: qup-i2c6-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio56", "gpio57";
+ function = "qup1_se6";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_i2c8_data_clk: qup-i2c8-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio0", "gpio1";
+ function = "qup2_se0";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_i2c9_data_clk: qup-i2c9-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio4", "gpio5";
+ function = "qup2_se1";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_i2c10_data_clk: qup-i2c10-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio8", "gpio9";
+ function = "qup2_se2";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_i2c11_data_clk: qup-i2c11-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio12", "gpio13";
+ function = "qup2_se3";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_i2c12_data_clk: qup-i2c12-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio16", "gpio17";
+ function = "qup2_se4";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_i2c13_data_clk: qup-i2c13-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio20", "gpio21";
+ function = "qup2_se5";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_i2c15_data_clk: qup-i2c15-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio28", "gpio29";
+ function = "qup2_se7";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_spi0_cs: qup-spi0-cs-state {
+ pins = "gpio35";
+ function = "qup1_se0";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi0_data_clk: qup-spi0-data-clk-state {
+ /* MISO, MOSI, CLK */
+ pins = "gpio32", "gpio33", "gpio34";
+ function = "qup1_se0";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi1_cs: qup-spi1-cs-state {
+ pins = "gpio39";
+ function = "qup1_se1";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi1_data_clk: qup-spi1-data-clk-state {
+ /* MISO, MOSI, CLK */
+ pins = "gpio36", "gpio37", "gpio38";
+ function = "qup1_se1";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi2_cs: qup-spi2-cs-state {
+ pins = "gpio43";
+ function = "qup1_se2";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi2_data_clk: qup-spi2-data-clk-state {
+ /* MISO, MOSI, CLK */
+ pins = "gpio40", "gpio41", "gpio42";
+ function = "qup1_se2";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi3_cs: qup-spi3-cs-state {
+ pins = "gpio47";
+ function = "qup1_se3";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi3_data_clk: qup-spi3-data-clk-state {
+ /* MISO, MOSI, CLK */
+ pins = "gpio44", "gpio45", "gpio46";
+ function = "qup1_se3";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi4_cs: qup-spi4-cs-state {
+ pins = "gpio51";
+ function = "qup1_se4";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi4_data_clk: qup-spi4-data-clk-state {
+ /* MISO, MOSI, CLK */
+ pins = "gpio48", "gpio49", "gpio50";
+ function = "qup1_se4";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi5_cs: qup-spi5-cs-state {
+ pins = "gpio55";
+ function = "qup1_se5";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi5_data_clk: qup-spi5-data-clk-state {
+ /* MISO, MOSI, CLK */
+ pins = "gpio52", "gpio53", "gpio54";
+ function = "qup1_se5";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi6_cs: qup-spi6-cs-state {
+ pins = "gpio59";
+ function = "qup1_se6";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi6_data_clk: qup-spi6-data-clk-state {
+ /* MISO, MOSI, CLK */
+ pins = "gpio56", "gpio57", "gpio58";
+ function = "qup1_se6";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi8_cs: qup-spi8-cs-state {
+ pins = "gpio3";
+ function = "qup2_se0";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi8_data_clk: qup-spi8-data-clk-state {
+ /* MISO, MOSI, CLK */
+ pins = "gpio0", "gpio1", "gpio2";
+ function = "qup2_se0";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi9_cs: qup-spi9-cs-state {
+ pins = "gpio7";
+ function = "qup2_se1";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi9_data_clk: qup-spi9-data-clk-state {
+ /* MISO, MOSI, CLK */
+ pins = "gpio4", "gpio5", "gpio6";
+ function = "qup2_se1";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi10_cs: qup-spi10-cs-state {
+ pins = "gpio11";
+ function = "qup2_se2";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi10_data_clk: qup-spi10-data-clk-state {
+ /* MISO, MOSI, CLK */
+ pins = "gpio8", "gpio9", "gpio10";
+ function = "qup2_se2";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi11_cs: qup-spi11-cs-state {
+ pins = "gpio15";
+ function = "qup2_se3";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi11_data_clk: qup-spi11-data-clk-state {
+ /* MISO, MOSI, CLK */
+ pins = "gpio12", "gpio13", "gpio14";
+ function = "qup2_se3";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi12_cs: qup-spi12-cs-state {
+ pins = "gpio19";
+ function = "qup2_se4";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi12_data_clk: qup-spi12-data-clk-state {
+ /* MISO, MOSI, CLK */
+ pins = "gpio16", "gpio17", "gpio18";
+ function = "qup2_se4";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi13_cs: qup-spi13-cs-state {
+ pins = "gpio23";
+ function = "qup2_se5";
+ drive-strength = <6>;
+ bias-pull-up;
+ };
+
+ qup_spi13_data_clk: qup-spi13-data-clk-state {
+ /* MISO, MOSI, CLK */
+ pins = "gpio20", "gpio21", "gpio22";
+ function = "qup2_se5";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi15_cs: qup-spi15-cs-state {
+ pins = "gpio31";
+ function = "qup2_se7";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi15_data_clk: qup-spi15-data-clk-state {
+ /* MISO, MOSI, CLK */
+ pins = "gpio28", "gpio29", "gpio30";
+ function = "qup2_se7";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_uart7_default: qup-uart7-default-state {
+ /* TX, RX */
+ pins = "gpio62", "gpio63";
+ function = "qup1_se7";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ qup_uart14_default: qup-uart14-default-state {
+ /* TX, RX */
+ pins = "gpio26", "gpio27";
+ function = "qup2_se6";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_uart14_cts_rts: qup-uart14-cts-rts-state {
+ /* CTS, RTS */
+ pins = "gpio24", "gpio25";
+ function = "qup2_se6";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ sdc2_sleep: sdc2-sleep-state {
+ clk-pins {
+ pins = "sdc2_clk";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ cmd-pins {
+ pins = "sdc2_cmd";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ data-pins {
+ pins = "sdc2_data";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ sdc2_default: sdc2-default-state {
+ clk-pins {
+ pins = "sdc2_clk";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ cmd-pins {
+ pins = "sdc2_cmd";
+ drive-strength = <10>;
+ bias-pull-up;
+ };
+
+ data-pins {
+ pins = "sdc2_data";
+ drive-strength = <10>;
+ bias-pull-up;
+ };
+ };
+ };
+
+ tcsrcc: clock-controller@f204008 {
+ compatible = "qcom,sm8750-tcsr", "syscon";
+ reg = <0x0 0xf204008 0x0 0x3004>;
+
+ clocks = <&rpmhcc RPMH_CXO_CLK>;
+
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ apps_smmu: iommu@15000000 {
+ compatible = "qcom,sm8750-smmu-500", "qcom,smmu-500", "arm,mmu-500";
+ reg = <0x0 0x15000000 0x0 0x100000>;
+
+ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 492 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 493 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 494 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 497 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 498 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 502 IRQ_TYPE_LEVEL_HIGH>;
+
+ #iommu-cells = <2>;
+ #global-interrupts = <1>;
+ };
+
+ intc: interrupt-controller@16000000 {
+ compatible = "arm,gic-v3";
+ reg = <0x0 0x16000000 0x0 0x10000>, /* GICD */
+ <0x0 0x16080000 0x0 0x200000>; /* GICR * 12 */
+
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+
+ #interrupt-cells = <3>;
+ interrupt-controller;
+
+ #redistributor-regions = <1>;
+ redistributor-stride = <0x0 0x40000>;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ gic_its: msi-controller@16040000 {
+ compatible = "arm,gic-v3-its";
+ reg = <0x0 0x16040000 0x0 0x20000>;
+
+ msi-controller;
+ #msi-cells = <1>;
+
+ status = "disabled";
+ };
+ };
+
+ apps_rsc: rsc@16500000 {
+ compatible = "qcom,rpmh-rsc";
+ reg = <0x0 0x16500000 0x0 0x10000>,
+ <0x0 0x16510000 0x0 0x10000>,
+ <0x0 0x16520000 0x0 0x10000>;
+ reg-names = "drv-0",
+ "drv-1",
+ "drv-2";
+ qcom,drv-count = <3>;
+
+ interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,tcs-offset = <0xd00>;
+ qcom,drv-id = <2>;
+ qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>,
+ <WAKE_TCS 2>, <CONTROL_TCS 0>;
+
+ label = "apps_rsc";
+
+ apps_bcm_voter: bcm-voter {
+ compatible = "qcom,bcm-voter";
+ };
+
+ rpmhcc: clock-controller {
+ compatible = "qcom,sm8750-rpmh-clk";
+
+ clocks = <&xo_board>;
+ clock-names = "xo";
+
+ #clock-cells = <1>;
+ };
+
+ rpmhpd: power-controller {
+ compatible = "qcom,sm8750-rpmhpd";
+
+ operating-points-v2 = <&rpmhpd_opp_table>;
+
+ #power-domain-cells = <1>;
+
+ rpmhpd_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ rpmhpd_opp_ret: opp-16 {
+ opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
+ };
+
+ rpmhpd_opp_min_svs: opp-48 {
+ opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
+ };
+
+ rpmhpd_opp_low_svs_d3: opp-50 {
+ opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D3>;
+ };
+
+ rpmhpd_opp_low_svs_d2: opp-52 {
+ opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
+ };
+
+ rpmhpd_opp_low_svs_d1: opp-56 {
+ opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
+ };
+
+ rpmhpd_opp_low_svs_d0: opp-60 {
+ opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
+ };
+
+ rpmhpd_opp_low_svs: opp-64 {
+ opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+ };
+
+ rpmhpd_opp_low_svs_l1: opp-80 {
+ opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
+ };
+
+ rpmhpd_opp_svs: opp-128 {
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
+ };
+
+ rpmhpd_opp_svs_l0: opp-144 {
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
+ };
+
+ rpmhpd_opp_svs_l1: opp-192 {
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+ };
+
+ rpmhpd_opp_svs_l2: opp-224 {
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
+ };
+
+ rpmhpd_opp_nom: opp-256 {
+ opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
+ };
+
+ rpmhpd_opp_nom_l1: opp-320 {
+ opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
+ };
+
+ rpmhpd_opp_nom_l2: opp-336 {
+ opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
+ };
+
+ rpmhpd_opp_turbo: opp-384 {
+ opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
+ };
+
+ rpmhpd_opp_turbo_l1: opp-416 {
+ opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
+ };
+
+ rpmhpd_opp_turbo_l2: opp-432 {
+ opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L2>;
+ };
+
+ rpmhpd_opp_turbo_l3: opp-448 {
+ opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L3>;
+ };
+
+ rpmhpd_opp_turbo_l4: opp-452 {
+ opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L4>;
+ };
+
+ rpmhpd_opp_super_turbo_no_cpr: opp-480 {
+ opp-level =
+ <RPMH_REGULATOR_LEVEL_SUPER_TURBO_NO_CPR>;
+ };
+ };
+ };
+ };
+
+ timer@16800000 {
+ compatible = "arm,armv7-timer-mem";
+ reg = <0x0 0x16800000 0x0 0x1000>;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ frame@16801000 {
+ reg = <0x0 0x16801000 0x0 0x1000>,
+ <0x0 0x16802000 0x0 0x1000>;
+
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+
+ frame-number = <0>;
+ };
+
+ frame@16803000 {
+ reg = <0x0 0x16803000 0x0 0x1000>;
+
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+
+ frame-number = <1>;
+
+ status = "disabled";
+ };
+
+ frame@16805000 {
+ reg = <0x0 0x16805000 0x0 0x1000>;
+
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+
+ frame-number = <2>;
+
+ status = "disabled";
+ };
+
+ frame@16807000 {
+ reg = <0x0 0x16807000 0x0 0x1000>;
+
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+
+ frame-number = <3>;
+
+ status = "disabled";
+ };
+
+ frame@16809000 {
+ reg = <0x0 0x16809000 0x0 0x1000>;
+
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+
+ frame-number = <4>;
+
+ status = "disabled";
+ };
+
+ frame@1680b000 {
+ reg = <0x0 0x1680b000 0x0 0x1000>;
+
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+
+ frame-number = <5>;
+
+ status = "disabled";
+ };
+
+ frame@1680d000 {
+ reg = <0x0 0x1680d000 0x0 0x1000>;
+
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+
+ frame-number = <6>;
+
+ status = "disabled";
+ };
+ };
+
+ gem_noc: interconnect@24100000 {
+ compatible = "qcom,sm8750-gem-noc";
+ reg = <0x0 0x24100000 0x0 0x14b080>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ #interconnect-cells = <2>;
+ };
+
+ nsp_noc: interconnect@320c0000 {
+ compatible = "qcom,sm8750-nsp-noc";
+ reg = <0x0 0x320c0000 0x0 0x13080>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ #interconnect-cells = <2>;
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
--
2.46.1
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 5/5] arm64: defconfig: Enable SM8750 SoC base configs
2024-10-21 23:21 [PATCH 0/5] dts: qcom: Introduce SM8750 device trees Melody Olvera
` (3 preceding siblings ...)
2024-10-21 23:21 ` [PATCH 4/5] arm64: dts: qcom: Add base sm8750 dtsi and mtp and qrd dts Melody Olvera
@ 2024-10-21 23:21 ` Melody Olvera
2024-10-23 8:31 ` Krzysztof Kozlowski
2024-10-24 16:33 ` [PATCH 0/5] dts: qcom: Introduce SM8750 device trees Rob Herring (Arm)
5 siblings, 1 reply; 18+ messages in thread
From: Melody Olvera @ 2024-10-21 23:21 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Lee Jones, Catalin Marinas, Will Deacon,
Geert Uytterhoeven, Dmitry Baryshkov, AngeloGioacchino Del Regno,
Neil Armstrong, Arnd Bergmann, Nícolas F . R . A . Prado,
Stephen Boyd, Trilok Soni, Satya Durga Srinivasu Prabhala
Cc: linux-arm-msm, devicetree, linux-kernel, linux-arm-kernel,
Melody Olvera, Raviteja Laggyshetty
Enable GCC, TCSRCC, Pinctrl and Interconnect configs for Qualcomm's
SM8750 SoC which is required to boot SM8750 MTP/QRD boards to a
console shell. The configs are required to be marked as builtin
and not modules due to the console driver dependencies.
Co-developed-by: Raviteja Laggyshetty <quic_rlaggysh@quicinc.com>
Signed-off-by: Raviteja Laggyshetty <quic_rlaggysh@quicinc.com>
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
---
arch/arm64/configs/defconfig | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 36b33b9f1704..9d6507412ee0 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -629,6 +629,7 @@ CONFIG_PINCTRL_SM8350=y
CONFIG_PINCTRL_SM8450=y
CONFIG_PINCTRL_SM8550=y
CONFIG_PINCTRL_SM8650=y
+CONFIG_PINCTRL_SM8750=y
CONFIG_PINCTRL_X1E80100=y
CONFIG_PINCTRL_QCOM_SPMI_PMIC=y
CONFIG_PINCTRL_LPASS_LPI=m
@@ -1357,6 +1358,7 @@ CONFIG_SM_GCC_8350=y
CONFIG_SM_GCC_8450=y
CONFIG_SM_GCC_8550=y
CONFIG_SM_GCC_8650=y
+CONFIG_SM_GCC_8750=y
CONFIG_SM_GPUCC_6115=m
CONFIG_SM_GPUCC_8150=y
CONFIG_SM_GPUCC_8250=y
@@ -1366,6 +1368,7 @@ CONFIG_SM_GPUCC_8550=m
CONFIG_SM_GPUCC_8650=m
CONFIG_SM_TCSRCC_8550=y
CONFIG_SM_TCSRCC_8650=y
+CONFIG_SM_TCSRCC_8750=y
CONFIG_SM_VIDEOCC_8250=y
CONFIG_QCOM_HFPLL=y
CONFIG_CLK_GFM_LPASS_SM8250=m
@@ -1644,6 +1647,7 @@ CONFIG_INTERCONNECT_QCOM_SM8350=y
CONFIG_INTERCONNECT_QCOM_SM8450=y
CONFIG_INTERCONNECT_QCOM_SM8550=y
CONFIG_INTERCONNECT_QCOM_SM8650=y
+CONFIG_INTERCONNECT_QCOM_SM8750=y
CONFIG_INTERCONNECT_QCOM_X1E80100=y
CONFIG_COUNTER=m
CONFIG_RZ_MTU3_CNT=m
--
2.46.1
^ permalink raw reply related [flat|nested] 18+ messages in thread
* Re: [PATCH 4/5] arm64: dts: qcom: Add base sm8750 dtsi and mtp and qrd dts
2024-10-21 23:21 ` [PATCH 4/5] arm64: dts: qcom: Add base sm8750 dtsi and mtp and qrd dts Melody Olvera
@ 2024-10-23 3:12 ` Bjorn Andersson
2024-10-23 21:58 ` Melody Olvera
2024-11-02 9:36 ` Konrad Dybcio
1 sibling, 1 reply; 18+ messages in thread
From: Bjorn Andersson @ 2024-10-23 3:12 UTC (permalink / raw)
To: Melody Olvera
Cc: Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Lee Jones, Catalin Marinas, Will Deacon, Geert Uytterhoeven,
Dmitry Baryshkov, AngeloGioacchino Del Regno, Neil Armstrong,
Arnd Bergmann, Nícolas F . R . A . Prado, Stephen Boyd,
Trilok Soni, Satya Durga Srinivasu Prabhala, linux-arm-msm,
devicetree, linux-kernel, linux-arm-kernel, Taniya Das,
Jishnu Prakash, Raviteja Laggyshetty
On Mon, Oct 21, 2024 at 04:21:13PM GMT, Melody Olvera wrote:
2 "and", 2 "dts" and a "dtsi" in the subject. I'd prefer a more
succinct:
"arm64: dts: qcom: Add SM8750 platform, mtp and qrd"
> Add base dtsi for the sm8750 SoC describing the CPUs, GCC and
> RPMHCC clock controllers, geni UART, interrupt controller, TLMM,
> reserved memory, interconnects, regulator, and SMMU nodes. Also add
> MTP and QRD board dts files for sm8750.
>
Nice.
> Co-developed-by: Taniya Das <quic_tdas@quicinc.com>
> Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
> Co-developed-by: Jishnu Prakash <quic_jprakash@quicinc.com>
> Signed-off-by: Jishnu Prakash <quic_jprakash@quicinc.com>
> Co-developed-by: Raviteja Laggyshetty <quic_rlaggysh@quicinc.com>
> Signed-off-by: Raviteja Laggyshetty <quic_rlaggysh@quicinc.com>
> Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
> ---
> arch/arm64/boot/dts/qcom/Makefile | 2 +
> arch/arm64/boot/dts/qcom/sm8750-mtp.dts | 968 ++++++++
> arch/arm64/boot/dts/qcom/sm8750-qrd.dts | 965 ++++++++
> arch/arm64/boot/dts/qcom/sm8750.dtsi | 2903 +++++++++++++++++++++++
> 4 files changed, 4838 insertions(+)
Most reviewers will prefer the platform and individual devices to be
added in separate patches, to not hit 5kloc. I don't mind it...
> create mode 100644 arch/arm64/boot/dts/qcom/sm8750-mtp.dts
> create mode 100644 arch/arm64/boot/dts/qcom/sm8750-qrd.dts
> create mode 100644 arch/arm64/boot/dts/qcom/sm8750.dtsi
>
> diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
> index 065bb19481c1..3bedfa6b37f2 100644
> --- a/arch/arm64/boot/dts/qcom/Makefile
> +++ b/arch/arm64/boot/dts/qcom/Makefile
> @@ -269,6 +269,8 @@ dtb-$(CONFIG_ARCH_QCOM) += sm8650-hdk-display-card.dtb
> dtb-$(CONFIG_ARCH_QCOM) += sm8650-hdk.dtb
> dtb-$(CONFIG_ARCH_QCOM) += sm8650-mtp.dtb
> dtb-$(CONFIG_ARCH_QCOM) += sm8650-qrd.dtb
> +dtb-$(CONFIG_ARCH_QCOM) += sm8750-mtp.dtb
> +dtb-$(CONFIG_ARCH_QCOM) += sm8750-qrd.dtb
> dtb-$(CONFIG_ARCH_QCOM) += x1e78100-lenovo-thinkpad-t14s.dtb
> dtb-$(CONFIG_ARCH_QCOM) += x1e80100-asus-vivobook-s15.dtb
> dtb-$(CONFIG_ARCH_QCOM) += x1e80100-crd.dtb
> diff --git a/arch/arm64/boot/dts/qcom/sm8750-mtp.dts b/arch/arm64/boot/dts/qcom/sm8750-mtp.dts
> new file mode 100644
> index 000000000000..e1a94dc76e2f
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/sm8750-mtp.dts
> @@ -0,0 +1,968 @@
> +// SPDX-License-Identifier: BSD-3-Clause
> +/*
> + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
> + */
> +
> +/dts-v1/;
> +
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/leds/common.h>
> +#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
> +#include "sm8750.dtsi"
> +#include "pm8010.dtsi"
> +#include "pm8550.dtsi"
> +#define PMK8550VE_SID 8
> +#include "pm8550ve.dtsi"
> +#include "pmd8028.dtsi"
> +#include "pmih0108.dtsi"
> +#include "pmk8550.dtsi"
> +#include "pmr735d_a.dtsi"
> +
> +/ {
> + model = "Qualcomm Technologies, Inc. SM8750 MTP";
> + compatible = "qcom,sm8750-mtp", "qcom,sm8750";
Can we please here have a:
chassis-type = "handset";
> +
[..]
> diff --git a/arch/arm64/boot/dts/qcom/sm8750-qrd.dts b/arch/arm64/boot/dts/qcom/sm8750-qrd.dts
> new file mode 100644
> index 000000000000..af0174d95e3a
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/sm8750-qrd.dts
> @@ -0,0 +1,965 @@
> +// SPDX-License-Identifier: BSD-3-Clause
> +/*
> + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
> + */
> +
> +/dts-v1/;
> +
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/leds/common.h>
> +#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
> +#include "sm8750.dtsi"
> +#include "pm8010.dtsi"
> +#include "pm8550.dtsi"
> +#define PMK8550VE_SID 8
> +#include "pm8550ve.dtsi"
> +#include "pmd8028.dtsi"
> +#include "pmih0108.dtsi"
> +#include "pmk8550.dtsi"
> +#include "pmr735d_a.dtsi"
> +
> +/ {
> + model = "Qualcomm Technologies, Inc. SM8750 QRD";
> + compatible = "qcom,sm8750-qrd", "qcom,sm8750";
chassis-type please.
> +
> + aliases {
> + serial0 = &uart7;
> + };
[..]
> diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi
> new file mode 100644
> index 000000000000..98ab82caa007
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi
> @@ -0,0 +1,2903 @@
> +// SPDX-License-Identifier: BSD-3-Clause
> +/*
> + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
> + */
> +
> +#include <dt-bindings/clock/qcom,rpmh.h>
> +#include <dt-bindings/clock/qcom,sm8750-gcc.h>
> +#include <dt-bindings/clock/qcom,sm8750-tcsr.h>
> +#include <dt-bindings/dma/qcom-gpi.h>
> +#include <dt-bindings/interconnect/qcom,icc.h>
> +#include <dt-bindings/interconnect/qcom,sm8750-rpmh.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/power/qcom,rpmhpd.h>
> +#include <dt-bindings/power/qcom-rpmpd.h>
> +#include <dt-bindings/soc/qcom,rpmh-rsc.h>
> +
> +/ {
> + interrupt-parent = <&intc>;
> +
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + chosen { };
You should be able to omit this...
> +
> + cpus {
> + #address-cells = <2>;
> + #size-cells = <0>;
> +
> + CPU0: cpu@0 {
I just merged a cleanup series from Krzysztof, making all labels lower
case. So, I'd unfortunately like you to do the same...
> + device_type = "cpu";
> + compatible = "qcom,oryon";
> + reg = <0x0 0x0>;
> + enable-method = "psci";
> + next-level-cache = <&L2_0>;
> + power-domains = <&CPU_PD0>;
> + power-domain-names = "psci";
> + cpu-idle-states = <&CLUSTER0_C4>;
> +
> + L2_0: l2-cache {
> + compatible = "cache";
> + cache-level = <2>;
> + cache-unified;
> + };
> + };
[..]
> + memory@a0000000 {
> + device_type = "memory";
> + /* We expect the bootloader to fill in the size */
> + reg = <0x0 0xa0000000 0x0 0x0>;
gunyah_hyp_mem below is at 0x80000000, so I presume it's not just size
that's being updated?
> + };
> +
[..]
> + soc: soc@0 {
[..]
> + };
> +
> +
Extra newline, didn't checkpatch --strict complain about that/
> + cnoc_main: interconnect@1500000 {
> + compatible = "qcom,sm8750-cnoc-main";
> + reg = <0x0 0x1500000 0x0 0x16080>;
Until here you padded the base address to 8 digits, making it easy for
humans to keep nodes sorted (by address). Please correct the remaining
7-digit nodes as well, to make it easier for future contributors to get
their ordering right.
> + qcom,bcm-voters = <&apps_bcm_voter>;
> + #interconnect-cells = <2>;
> + };
> +
> + config_noc: interconnect@1600000 {
> + compatible = "qcom,sm8750-cnoc-cfg";
> + reg = <0x0 0x1600000 0x0 0x6200>;
> + qcom,bcm-voters = <&apps_bcm_voter>;
> + #interconnect-cells = <2>;
> + };
[..]
> + apps_rsc: rsc@16500000 {
> + compatible = "qcom,rpmh-rsc";
> + reg = <0x0 0x16500000 0x0 0x10000>,
> + <0x0 0x16510000 0x0 0x10000>,
> + <0x0 0x16520000 0x0 0x10000>;
> + reg-names = "drv-0",
> + "drv-1",
> + "drv-2";
> + qcom,drv-count = <3>;
> +
> + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
> + qcom,tcs-offset = <0xd00>;
> + qcom,drv-id = <2>;
> + qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>,
> + <WAKE_TCS 2>, <CONTROL_TCS 0>;
Is 0 CONTROL_TCSs correct?
> +
> + label = "apps_rsc";
> +
Regards,
Bjorn
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 1/5] dt-bindings: arm: qcom: Document sm8750 SoC and boards
2024-10-21 23:21 ` [PATCH 1/5] dt-bindings: arm: qcom: Document sm8750 SoC and boards Melody Olvera
@ 2024-10-23 8:29 ` Krzysztof Kozlowski
0 siblings, 0 replies; 18+ messages in thread
From: Krzysztof Kozlowski @ 2024-10-23 8:29 UTC (permalink / raw)
To: Melody Olvera
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Lee Jones, Catalin Marinas, Will Deacon,
Geert Uytterhoeven, Dmitry Baryshkov, AngeloGioacchino Del Regno,
Neil Armstrong, Arnd Bergmann, Nícolas F . R . A . Prado,
Stephen Boyd, Trilok Soni, Satya Durga Srinivasu Prabhala,
linux-arm-msm, devicetree, linux-kernel, linux-arm-kernel
On Mon, Oct 21, 2024 at 04:21:10PM -0700, Melody Olvera wrote:
> Document the SM8750 SoC binding and the boards which use it.
>
> Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
> ---
> Documentation/devicetree/bindings/arm/qcom.yaml | 7 +++++++
> 1 file changed, 7 insertions(+)
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 2/5] dt-bindings: mfd: qcom,spmi-pmic: Document PMICs added in SM8750
2024-10-21 23:21 ` [PATCH 2/5] dt-bindings: mfd: qcom,spmi-pmic: Document PMICs added in SM8750 Melody Olvera
@ 2024-10-23 8:30 ` Krzysztof Kozlowski
2024-11-01 15:56 ` (subset) " Lee Jones
1 sibling, 0 replies; 18+ messages in thread
From: Krzysztof Kozlowski @ 2024-10-23 8:30 UTC (permalink / raw)
To: Melody Olvera
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Lee Jones, Catalin Marinas, Will Deacon,
Geert Uytterhoeven, Dmitry Baryshkov, AngeloGioacchino Del Regno,
Neil Armstrong, Arnd Bergmann, Nícolas F . R . A . Prado,
Stephen Boyd, Trilok Soni, Satya Durga Srinivasu Prabhala,
linux-arm-msm, devicetree, linux-kernel, linux-arm-kernel,
Jishnu Prakash
On Mon, Oct 21, 2024 at 04:21:11PM -0700, Melody Olvera wrote:
> From: Jishnu Prakash <quic_jprakash@quicinc.com>
>
> Document compatibles for the added pmd8028 and pmih0108 SPMI PMICs.
>
> Signed-off-by: Jishnu Prakash <quic_jprakash@quicinc.com>
> Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
> ---
> Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml | 2 ++
> 1 file changed, 2 insertions(+)
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 5/5] arm64: defconfig: Enable SM8750 SoC base configs
2024-10-21 23:21 ` [PATCH 5/5] arm64: defconfig: Enable SM8750 SoC base configs Melody Olvera
@ 2024-10-23 8:31 ` Krzysztof Kozlowski
0 siblings, 0 replies; 18+ messages in thread
From: Krzysztof Kozlowski @ 2024-10-23 8:31 UTC (permalink / raw)
To: Melody Olvera
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Lee Jones, Catalin Marinas, Will Deacon,
Geert Uytterhoeven, Dmitry Baryshkov, AngeloGioacchino Del Regno,
Neil Armstrong, Arnd Bergmann, Nícolas F . R . A . Prado,
Stephen Boyd, Trilok Soni, Satya Durga Srinivasu Prabhala,
linux-arm-msm, devicetree, linux-kernel, linux-arm-kernel,
Raviteja Laggyshetty
On Mon, Oct 21, 2024 at 04:21:14PM -0700, Melody Olvera wrote:
> Enable GCC, TCSRCC, Pinctrl and Interconnect configs for Qualcomm's
> SM8750 SoC which is required to boot SM8750 MTP/QRD boards to a
> console shell. The configs are required to be marked as builtin
> and not modules due to the console driver dependencies.
>
> Co-developed-by: Raviteja Laggyshetty <quic_rlaggysh@quicinc.com>
> Signed-off-by: Raviteja Laggyshetty <quic_rlaggysh@quicinc.com>
> Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
> ---
> arch/arm64/configs/defconfig | 4 ++++
> 1 file changed, 4 insertions(+)
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 4/5] arm64: dts: qcom: Add base sm8750 dtsi and mtp and qrd dts
2024-10-23 3:12 ` Bjorn Andersson
@ 2024-10-23 21:58 ` Melody Olvera
0 siblings, 0 replies; 18+ messages in thread
From: Melody Olvera @ 2024-10-23 21:58 UTC (permalink / raw)
To: Bjorn Andersson
Cc: Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Lee Jones, Catalin Marinas, Will Deacon, Geert Uytterhoeven,
Dmitry Baryshkov, AngeloGioacchino Del Regno, Neil Armstrong,
Arnd Bergmann, Nícolas F . R . A . Prado, Stephen Boyd,
Trilok Soni, Satya Durga Srinivasu Prabhala, linux-arm-msm,
devicetree, linux-kernel, linux-arm-kernel, Taniya Das,
Jishnu Prakash, Raviteja Laggyshetty
On 10/22/2024 8:12 PM, Bjorn Andersson wrote:
> On Mon, Oct 21, 2024 at 04:21:13PM GMT, Melody Olvera wrote:
>
> 2 "and", 2 "dts" and a "dtsi" in the subject. I'd prefer a more
> succinct:
>
> "arm64: dts: qcom: Add SM8750 platform, mtp and qrd"
Ack.
>
>> Add base dtsi for the sm8750 SoC describing the CPUs, GCC and
>> RPMHCC clock controllers, geni UART, interrupt controller, TLMM,
>> reserved memory, interconnects, regulator, and SMMU nodes. Also add
>> MTP and QRD board dts files for sm8750.
>>
> Nice.
>
>> Co-developed-by: Taniya Das <quic_tdas@quicinc.com>
>> Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
>> Co-developed-by: Jishnu Prakash <quic_jprakash@quicinc.com>
>> Signed-off-by: Jishnu Prakash <quic_jprakash@quicinc.com>
>> Co-developed-by: Raviteja Laggyshetty <quic_rlaggysh@quicinc.com>
>> Signed-off-by: Raviteja Laggyshetty <quic_rlaggysh@quicinc.com>
>> Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
>> ---
>> arch/arm64/boot/dts/qcom/Makefile | 2 +
>> arch/arm64/boot/dts/qcom/sm8750-mtp.dts | 968 ++++++++
>> arch/arm64/boot/dts/qcom/sm8750-qrd.dts | 965 ++++++++
>> arch/arm64/boot/dts/qcom/sm8750.dtsi | 2903 +++++++++++++++++++++++
>> 4 files changed, 4838 insertions(+)
> Most reviewers will prefer the platform and individual devices to be
> added in separate patches, to not hit 5kloc. I don't mind it...
I wasn't sure whether or not to split; some recent efforts had combined
platform
and devices into one patch. Either works for me.
>
>> create mode 100644 arch/arm64/boot/dts/qcom/sm8750-mtp.dts
>> create mode 100644 arch/arm64/boot/dts/qcom/sm8750-qrd.dts
>> create mode 100644 arch/arm64/boot/dts/qcom/sm8750.dtsi
>>
>> diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
>> index 065bb19481c1..3bedfa6b37f2 100644
>> --- a/arch/arm64/boot/dts/qcom/Makefile
>> +++ b/arch/arm64/boot/dts/qcom/Makefile
>> @@ -269,6 +269,8 @@ dtb-$(CONFIG_ARCH_QCOM) += sm8650-hdk-display-card.dtb
>> dtb-$(CONFIG_ARCH_QCOM) += sm8650-hdk.dtb
>> dtb-$(CONFIG_ARCH_QCOM) += sm8650-mtp.dtb
>> dtb-$(CONFIG_ARCH_QCOM) += sm8650-qrd.dtb
>> +dtb-$(CONFIG_ARCH_QCOM) += sm8750-mtp.dtb
>> +dtb-$(CONFIG_ARCH_QCOM) += sm8750-qrd.dtb
>> dtb-$(CONFIG_ARCH_QCOM) += x1e78100-lenovo-thinkpad-t14s.dtb
>> dtb-$(CONFIG_ARCH_QCOM) += x1e80100-asus-vivobook-s15.dtb
>> dtb-$(CONFIG_ARCH_QCOM) += x1e80100-crd.dtb
>> diff --git a/arch/arm64/boot/dts/qcom/sm8750-mtp.dts b/arch/arm64/boot/dts/qcom/sm8750-mtp.dts
>> new file mode 100644
>> index 000000000000..e1a94dc76e2f
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/qcom/sm8750-mtp.dts
>> @@ -0,0 +1,968 @@
>> +// SPDX-License-Identifier: BSD-3-Clause
>> +/*
>> + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
>> + */
>> +
>> +/dts-v1/;
>> +
>> +#include <dt-bindings/gpio/gpio.h>
>> +#include <dt-bindings/leds/common.h>
>> +#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
>> +#include "sm8750.dtsi"
>> +#include "pm8010.dtsi"
>> +#include "pm8550.dtsi"
>> +#define PMK8550VE_SID 8
>> +#include "pm8550ve.dtsi"
>> +#include "pmd8028.dtsi"
>> +#include "pmih0108.dtsi"
>> +#include "pmk8550.dtsi"
>> +#include "pmr735d_a.dtsi"
>> +
>> +/ {
>> + model = "Qualcomm Technologies, Inc. SM8750 MTP";
>> + compatible = "qcom,sm8750-mtp", "qcom,sm8750";
> Can we please here have a:
>
> chassis-type = "handset";
Ack.
>
>> +
> [..]
>> diff --git a/arch/arm64/boot/dts/qcom/sm8750-qrd.dts b/arch/arm64/boot/dts/qcom/sm8750-qrd.dts
>> new file mode 100644
>> index 000000000000..af0174d95e3a
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/qcom/sm8750-qrd.dts
>> @@ -0,0 +1,965 @@
>> +// SPDX-License-Identifier: BSD-3-Clause
>> +/*
>> + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
>> + */
>> +
>> +/dts-v1/;
>> +
>> +#include <dt-bindings/gpio/gpio.h>
>> +#include <dt-bindings/leds/common.h>
>> +#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
>> +#include "sm8750.dtsi"
>> +#include "pm8010.dtsi"
>> +#include "pm8550.dtsi"
>> +#define PMK8550VE_SID 8
>> +#include "pm8550ve.dtsi"
>> +#include "pmd8028.dtsi"
>> +#include "pmih0108.dtsi"
>> +#include "pmk8550.dtsi"
>> +#include "pmr735d_a.dtsi"
>> +
>> +/ {
>> + model = "Qualcomm Technologies, Inc. SM8750 QRD";
>> + compatible = "qcom,sm8750-qrd", "qcom,sm8750";
> chassis-type please.
Ack.
>
>> +
>> + aliases {
>> + serial0 = &uart7;
>> + };
> [..]
>> diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi
>> new file mode 100644
>> index 000000000000..98ab82caa007
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi
>> @@ -0,0 +1,2903 @@
>> +// SPDX-License-Identifier: BSD-3-Clause
>> +/*
>> + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
>> + */
>> +
>> +#include <dt-bindings/clock/qcom,rpmh.h>
>> +#include <dt-bindings/clock/qcom,sm8750-gcc.h>
>> +#include <dt-bindings/clock/qcom,sm8750-tcsr.h>
>> +#include <dt-bindings/dma/qcom-gpi.h>
>> +#include <dt-bindings/interconnect/qcom,icc.h>
>> +#include <dt-bindings/interconnect/qcom,sm8750-rpmh.h>
>> +#include <dt-bindings/interrupt-controller/arm-gic.h>
>> +#include <dt-bindings/power/qcom,rpmhpd.h>
>> +#include <dt-bindings/power/qcom-rpmpd.h>
>> +#include <dt-bindings/soc/qcom,rpmh-rsc.h>
>> +
>> +/ {
>> + interrupt-parent = <&intc>;
>> +
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> +
>> + chosen { };
> You should be able to omit this...
Ack.
>
>> +
>> + cpus {
>> + #address-cells = <2>;
>> + #size-cells = <0>;
>> +
>> + CPU0: cpu@0 {
> I just merged a cleanup series from Krzysztof, making all labels lower
> case. So, I'd unfortunately like you to do the same...
Understood.
>
>> + device_type = "cpu";
>> + compatible = "qcom,oryon";
>> + reg = <0x0 0x0>;
>> + enable-method = "psci";
>> + next-level-cache = <&L2_0>;
>> + power-domains = <&CPU_PD0>;
>> + power-domain-names = "psci";
>> + cpu-idle-states = <&CLUSTER0_C4>;
>> +
>> + L2_0: l2-cache {
>> + compatible = "cache";
>> + cache-level = <2>;
>> + cache-unified;
>> + };
>> + };
> [..]
>> + memory@a0000000 {
>> + device_type = "memory";
>> + /* We expect the bootloader to fill in the size */
>> + reg = <0x0 0xa0000000 0x0 0x0>;
> gunyah_hyp_mem below is at 0x80000000, so I presume it's not just size
> that's being updated?
Yes; I believe it adds some more regions as well.
>
>> + };
>> +
> [..]
>> + soc: soc@0 {
> [..]
>> + };
>> +
>> +
> Extra newline, didn't checkpatch --strict complain about that/
Didn't realize I needed to run w --strict; will remove extra line.
>
>> + cnoc_main: interconnect@1500000 {
>> + compatible = "qcom,sm8750-cnoc-main";
>> + reg = <0x0 0x1500000 0x0 0x16080>;
> Until here you padded the base address to 8 digits, making it easy for
> humans to keep nodes sorted (by address). Please correct the remaining
> 7-digit nodes as well, to make it easier for future contributors to get
> their ordering right.
Will do.
>
>> + qcom,bcm-voters = <&apps_bcm_voter>;
>> + #interconnect-cells = <2>;
>> + };
>> +
>> + config_noc: interconnect@1600000 {
>> + compatible = "qcom,sm8750-cnoc-cfg";
>> + reg = <0x0 0x1600000 0x0 0x6200>;
>> + qcom,bcm-voters = <&apps_bcm_voter>;
>> + #interconnect-cells = <2>;
>> + };
> [..]
>> + apps_rsc: rsc@16500000 {
>> + compatible = "qcom,rpmh-rsc";
>> + reg = <0x0 0x16500000 0x0 0x10000>,
>> + <0x0 0x16510000 0x0 0x10000>,
>> + <0x0 0x16520000 0x0 0x10000>;
>> + reg-names = "drv-0",
>> + "drv-1",
>> + "drv-2";
>> + qcom,drv-count = <3>;
>> +
>> + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
>> + qcom,tcs-offset = <0xd00>;
>> + qcom,drv-id = <2>;
>> + qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>,
>> + <WAKE_TCS 2>, <CONTROL_TCS 0>;
> Is 0 CONTROL_TCSs correct?
I believe so; I have no reason to think otherwise.
Thanks,
Melody
>
>> +
>> + label = "apps_rsc";
>> +
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 0/5] dts: qcom: Introduce SM8750 device trees
2024-10-21 23:21 [PATCH 0/5] dts: qcom: Introduce SM8750 device trees Melody Olvera
` (4 preceding siblings ...)
2024-10-21 23:21 ` [PATCH 5/5] arm64: defconfig: Enable SM8750 SoC base configs Melody Olvera
@ 2024-10-24 16:33 ` Rob Herring (Arm)
2024-10-24 17:22 ` Konrad Dybcio
5 siblings, 1 reply; 18+ messages in thread
From: Rob Herring (Arm) @ 2024-10-24 16:33 UTC (permalink / raw)
To: Melody Olvera
Cc: Arnd Bergmann, Dmitry Baryshkov, Nícolas F . R . A . Prado,
linux-arm-kernel, devicetree, linux-kernel,
Satya Durga Srinivasu Prabhala, Trilok Soni,
AngeloGioacchino Del Regno, Neil Armstrong, Lee Jones,
Konrad Dybcio, Conor Dooley, Stephen Boyd, Krzysztof Kozlowski,
Bjorn Andersson, linux-arm-msm, Catalin Marinas,
Geert Uytterhoeven, Will Deacon
On Mon, 21 Oct 2024 16:21:09 -0700, Melody Olvera wrote:
> This series adds the initial device tree support for the SM8750 SoCs
> needed to boot to shell. This specifically adds support for clocks,
> pinctrl, rpmhpd, regulators, interconnects, and SoC and board
> compatibles.
>
> The Qualcomm Technologies, Inc. SM8750 SoC is the latest in the line of
> consumer mobile device SoCs. See more at:
> https://www.qualcomm.com/content/dam/qcomm-martech/dm-assets/images/company/news-media/media-center/press-kits/snapdragon-summit-2024/day-1/documents/Snapdragon8EliteProductBrief.pdf
>
> Dependencies:
> clks: https://lore.kernel.org/all/20241021230359.2632414-1-quic_molvera@quicinc.com/
> interconnects: https://lore.kernel.org/all/20241021231823.2635534-1-quic_molvera@quicinc.com/
> pinctrl: https://lore.kernel.org/all/20241021230414.2632428-1-quic_molvera@quicinc.com/
> regulators: https://lore.kernel.org/all/20241021230348.2632381-1-quic_molvera@quicinc.com/
> power domains: https://lore.kernel.org/all/20241021230333.2632368-1-quic_molvera@quicinc.com/
> misc bindings:
> - https://lore.kernel.org/all/20241021230427.2632466-1-quic_molvera@quicinc.com/
> - https://lore.kernel.org/all/20241021230500.2632527-1-quic_molvera@quicinc.com/
> - https://lore.kernel.org/all/20241021230439.2632480-1-quic_molvera@quicinc.com/
> - https://lore.kernel.org/all/20241021230449.2632493-1-quic_molvera@quicinc.com/
>
> Jishnu Prakash (2):
> dt-bindings: mfd: qcom,spmi-pmic: Document PMICs added in SM8750
> arm64: dts: qcom: Add pmd8028 and pmih0108 PMIC dtsi files
>
> Melody Olvera (3):
> dt-bindings: arm: qcom: Document sm8750 SoC and boards
> arm64: dts: qcom: Add base sm8750 dtsi and mtp and qrd dts
> arm64: defconfig: Enable SM8750 SoC base configs
>
> .../devicetree/bindings/arm/qcom.yaml | 7 +
> .../bindings/mfd/qcom,spmi-pmic.yaml | 2 +
> arch/arm64/boot/dts/qcom/Makefile | 2 +
> arch/arm64/boot/dts/qcom/pmd8028.dtsi | 56 +
> arch/arm64/boot/dts/qcom/pmih0108.dtsi | 62 +
> arch/arm64/boot/dts/qcom/sm8750-mtp.dts | 968 ++++++
> arch/arm64/boot/dts/qcom/sm8750-qrd.dts | 965 ++++++
> arch/arm64/boot/dts/qcom/sm8750.dtsi | 2903 +++++++++++++++++
> arch/arm64/configs/defconfig | 4 +
> 9 files changed, 4969 insertions(+)
> create mode 100644 arch/arm64/boot/dts/qcom/pmd8028.dtsi
> create mode 100644 arch/arm64/boot/dts/qcom/pmih0108.dtsi
> create mode 100644 arch/arm64/boot/dts/qcom/sm8750-mtp.dts
> create mode 100644 arch/arm64/boot/dts/qcom/sm8750-qrd.dts
> create mode 100644 arch/arm64/boot/dts/qcom/sm8750.dtsi
>
>
> base-commit: 63b3ff03d91ae8f875fe8747c781a521f78cde17
> prerequisite-patch-id: 5a4ad7a91dffc1c63a6513736cab88404937bbc5
> prerequisite-patch-id: f98e160b22d065fef3919e807102619ef80a63fd
> prerequisite-patch-id: 9df63975d51d61db536e843f261f837de613c0bb
> prerequisite-patch-id: dca6974344b25b6160e6a2680c438bc59da33374
> prerequisite-patch-id: 36ad7b3a06074897abcbe9521452ed0ec632e2eb
> prerequisite-patch-id: 255b9f24b2765ad6bb8fd5213b620ba2263d48f7
> prerequisite-patch-id: f458aa6a3d53924449be96609a0d1e65ec9f4854
> prerequisite-patch-id: 5bc1ec8226b52170508fd5ac30e31fec72e86f5a
> prerequisite-patch-id: 2b556803a12148cc12c1edcb5e143a454679a047
> prerequisite-patch-id: 0924872ce84c0f0011d53e98e58bf61213e9df43
> prerequisite-patch-id: 3a6538f98c3ce876d8acf3a0c55ac04897cfaf43
> prerequisite-patch-id: 7e047c63eff592833642eae37492b09e1ea7ed2d
> prerequisite-patch-id: cf8bef95f79c460b5b1c231a1122aa0173807a4d
> prerequisite-patch-id: ba4dd339acd73f885fe3d5f018ac620997583599
> prerequisite-patch-id: 5b930049e39fbd1ace2562d7870c2af764fe4cd4
> prerequisite-patch-id: 58acef79b9bf6c2e7d69d598d24502787eddc910
> prerequisite-patch-id: 369d52ee563f34eeca4a9c36e6d2b36b24eac635
> prerequisite-patch-id: e02a35925d37a2e61abbf240cc8963208f54e1c0
> prerequisite-patch-id: e4bf91d9a22d34c567eeab5b0f6fb90913ee908b
> --
> 2.46.1
>
>
>
My bot found new DTB warnings on the .dts files added or changed in this
series.
Some warnings may be from an existing SoC .dtsi. Or perhaps the warnings
are fixed by another series. Ultimately, it is up to the platform
maintainer whether these warnings are acceptable or not. No need to reply
unless the platform maintainer has comments.
If you already ran DT checks and didn't see these error(s), then
make sure dt-schema is up to date:
pip3 install dtschema --upgrade
New warnings running 'make CHECK_DTBS=y qcom/sm8750-mtp.dtb qcom/sm8750-qrd.dtb' for 20241021232114.2636083-1-quic_molvera@quicinc.com:
arch/arm64/boot/dts/qcom/sm8750-mtp.dtb: domain-idle-states: cluster-sleep-0: 'idle-state-name' does not match any of the regexes: 'pinctrl-[0-9]+'
from schema $id: http://devicetree.org/schemas/power/domain-idle-state.yaml#
arch/arm64/boot/dts/qcom/sm8750-mtp.dtb: domain-idle-states: cluster-sleep-0:compatible:0: 'domain-idle-state' was expected
from schema $id: http://devicetree.org/schemas/power/domain-idle-state.yaml#
arch/arm64/boot/dts/qcom/sm8750-qrd.dtb: domain-idle-states: cluster-sleep-0: 'idle-state-name' does not match any of the regexes: 'pinctrl-[0-9]+'
from schema $id: http://devicetree.org/schemas/power/domain-idle-state.yaml#
arch/arm64/boot/dts/qcom/sm8750-qrd.dtb: domain-idle-states: cluster-sleep-0:compatible:0: 'domain-idle-state' was expected
from schema $id: http://devicetree.org/schemas/power/domain-idle-state.yaml#
arch/arm64/boot/dts/qcom/sm8750-mtp.dtb: pmic@7: 'eusb2-repeater@fd00' does not match any of the regexes: '(.*)?(wled|leds)@[0-9a-f]+$', '^adc-tm@[0-9a-f]+$', '^adc@[0-9a-f]+$', '^audio-codec@[0-9a-f]+$', '^battery@[0-9a-f]+$', '^charger@[0-9a-f]+$', '^led-controller@[0-9a-f]+$', '^mpps@[0-9a-f]+$', '^nvram@[0-9a-f]+$', '^pbs@[0-9a-f]+$', '^rtc@[0-9a-f]+$', '^temp-alarm@[0-9a-f]+$', '^typec@[0-9a-f]+$', '^usb-detect@[0-9a-f]+$', '^usb-vbus-regulator@[0-9a-f]+$', '^vibrator@[0-9a-f]+$', 'gpio@[0-9a-f]+$', 'phy@[0-9a-f]+$', 'pinctrl-[0-9]+', 'pon@[0-9a-f]+$'
from schema $id: http://devicetree.org/schemas/mfd/qcom,spmi-pmic.yaml#
arch/arm64/boot/dts/qcom/sm8750-qrd.dtb: pmic@7: 'eusb2-repeater@fd00' does not match any of the regexes: '(.*)?(wled|leds)@[0-9a-f]+$', '^adc-tm@[0-9a-f]+$', '^adc@[0-9a-f]+$', '^audio-codec@[0-9a-f]+$', '^battery@[0-9a-f]+$', '^charger@[0-9a-f]+$', '^led-controller@[0-9a-f]+$', '^mpps@[0-9a-f]+$', '^nvram@[0-9a-f]+$', '^pbs@[0-9a-f]+$', '^rtc@[0-9a-f]+$', '^temp-alarm@[0-9a-f]+$', '^typec@[0-9a-f]+$', '^usb-detect@[0-9a-f]+$', '^usb-vbus-regulator@[0-9a-f]+$', '^vibrator@[0-9a-f]+$', 'gpio@[0-9a-f]+$', 'phy@[0-9a-f]+$', 'pinctrl-[0-9]+', 'pon@[0-9a-f]+$'
from schema $id: http://devicetree.org/schemas/mfd/qcom,spmi-pmic.yaml#
arch/arm64/boot/dts/qcom/sm8750-mtp.dtb: rsc@16500000: regulators-0: Unevaluated properties are not allowed ('vdd-l1-supply', 'vdd-l10-supply', 'vdd-l4-supply' were unexpected)
from schema $id: http://devicetree.org/schemas/soc/qcom/qcom,rpmh-rsc.yaml#
arch/arm64/boot/dts/qcom/sm8750-mtp.dtb: rsc@16500000: regulators-0: Unevaluated properties are not allowed ('vdd-l1-supply', 'vdd-l10-supply', 'vdd-l4-supply' were unexpected)
from schema $id: http://devicetree.org/schemas/soc/qcom/qcom,rpmh-rsc.yaml#
arch/arm64/boot/dts/qcom/sm8750-mtp.dtb: rsc@16500000: regulators-4: Unevaluated properties are not allowed ('vdd-s7-supply', 'vdd-s8-supply' were unexpected)
from schema $id: http://devicetree.org/schemas/soc/qcom/qcom,rpmh-rsc.yaml#
arch/arm64/boot/dts/qcom/sm8750-mtp.dtb: rsc@16500000: regulators-4: Unevaluated properties are not allowed ('vdd-s7-supply', 'vdd-s8-supply' were unexpected)
from schema $id: http://devicetree.org/schemas/soc/qcom/qcom,rpmh-rsc.yaml#
arch/arm64/boot/dts/qcom/sm8750-mtp.dtb: rsc@16500000: 'power-domains' is a required property
from schema $id: http://devicetree.org/schemas/soc/qcom/qcom,rpmh-rsc.yaml#
arch/arm64/boot/dts/qcom/sm8750-mtp.dtb: rsc@16500000: 'qcom,drv-count' does not match any of the regexes: '^regulators(-[0-9])?$', 'pinctrl-[0-9]+'
from schema $id: http://devicetree.org/schemas/soc/qcom/qcom,rpmh-rsc.yaml#
arch/arm64/boot/dts/qcom/sm8750-qrd.dtb: rsc@16500000: regulators-0: Unevaluated properties are not allowed ('vdd-l10-supply' was unexpected)
from schema $id: http://devicetree.org/schemas/soc/qcom/qcom,rpmh-rsc.yaml#
arch/arm64/boot/dts/qcom/sm8750-qrd.dtb: rsc@16500000: regulators-0: Unevaluated properties are not allowed ('vdd-l10-supply' was unexpected)
from schema $id: http://devicetree.org/schemas/soc/qcom/qcom,rpmh-rsc.yaml#
arch/arm64/boot/dts/qcom/sm8750-qrd.dtb: rsc@16500000: regulators-4: Unevaluated properties are not allowed ('vdd-s7-supply', 'vdd-s8-supply' were unexpected)
from schema $id: http://devicetree.org/schemas/soc/qcom/qcom,rpmh-rsc.yaml#
arch/arm64/boot/dts/qcom/sm8750-qrd.dtb: rsc@16500000: regulators-4: Unevaluated properties are not allowed ('vdd-s7-supply', 'vdd-s8-supply' were unexpected)
from schema $id: http://devicetree.org/schemas/soc/qcom/qcom,rpmh-rsc.yaml#
arch/arm64/boot/dts/qcom/sm8750-qrd.dtb: rsc@16500000: 'power-domains' is a required property
from schema $id: http://devicetree.org/schemas/soc/qcom/qcom,rpmh-rsc.yaml#
arch/arm64/boot/dts/qcom/sm8750-qrd.dtb: rsc@16500000: 'qcom,drv-count' does not match any of the regexes: '^regulators(-[0-9])?$', 'pinctrl-[0-9]+'
from schema $id: http://devicetree.org/schemas/soc/qcom/qcom,rpmh-rsc.yaml#
arch/arm64/boot/dts/qcom/sm8750-mtp.dtb: regulators-0: Unevaluated properties are not allowed ('vdd-l1-supply', 'vdd-l10-supply', 'vdd-l4-supply' were unexpected)
from schema $id: http://devicetree.org/schemas/regulator/qcom,rpmh-regulator.yaml#
arch/arm64/boot/dts/qcom/sm8750-qrd.dtb: regulators-0: Unevaluated properties are not allowed ('vdd-l10-supply' was unexpected)
from schema $id: http://devicetree.org/schemas/regulator/qcom,rpmh-regulator.yaml#
arch/arm64/boot/dts/qcom/sm8750-mtp.dtb: regulators-4: Unevaluated properties are not allowed ('vdd-s7-supply', 'vdd-s8-supply' were unexpected)
from schema $id: http://devicetree.org/schemas/regulator/qcom,rpmh-regulator.yaml#
arch/arm64/boot/dts/qcom/sm8750-qrd.dtb: regulators-4: Unevaluated properties are not allowed ('vdd-s7-supply', 'vdd-s8-supply' were unexpected)
from schema $id: http://devicetree.org/schemas/regulator/qcom,rpmh-regulator.yaml#
arch/arm64/boot/dts/qcom/sm8750-mtp.dtb: timer@16800000: #size-cells: 1 was expected
from schema $id: http://devicetree.org/schemas/timer/arm,arch_timer_mmio.yaml#
arch/arm64/boot/dts/qcom/sm8750-qrd.dtb: timer@16800000: #size-cells: 1 was expected
from schema $id: http://devicetree.org/schemas/timer/arm,arch_timer_mmio.yaml#
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 0/5] dts: qcom: Introduce SM8750 device trees
2024-10-24 16:33 ` [PATCH 0/5] dts: qcom: Introduce SM8750 device trees Rob Herring (Arm)
@ 2024-10-24 17:22 ` Konrad Dybcio
2024-10-24 22:46 ` Melody Olvera
0 siblings, 1 reply; 18+ messages in thread
From: Konrad Dybcio @ 2024-10-24 17:22 UTC (permalink / raw)
To: Rob Herring (Arm), Melody Olvera
Cc: Arnd Bergmann, Dmitry Baryshkov, Nícolas F . R . A . Prado,
linux-arm-kernel, devicetree, linux-kernel,
Satya Durga Srinivasu Prabhala, Trilok Soni,
AngeloGioacchino Del Regno, Neil Armstrong, Lee Jones,
Konrad Dybcio, Conor Dooley, Stephen Boyd, Krzysztof Kozlowski,
Bjorn Andersson, linux-arm-msm, Catalin Marinas,
Geert Uytterhoeven, Will Deacon
On 24.10.2024 6:33 PM, Rob Herring (Arm) wrote:
>
> On Mon, 21 Oct 2024 16:21:09 -0700, Melody Olvera wrote:
>> This series adds the initial device tree support for the SM8750 SoCs
>> needed to boot to shell. This specifically adds support for clocks,
>> pinctrl, rpmhpd, regulators, interconnects, and SoC and board
>> compatibles.
>>
[...]
> New warnings running 'make CHECK_DTBS=y qcom/sm8750-mtp.dtb qcom/sm8750-qrd.dtb' for 20241021232114.2636083-1-quic_molvera@quicinc.com:
>
> arch/arm64/boot/dts/qcom/sm8750-mtp.dtb: domain-idle-states: cluster-sleep-0: 'idle-state-name' does not match any of the regexes: 'pinctrl-[0-9]+'
> from schema $id: http://devicetree.org/schemas/power/domain-idle-state.yaml#
> arch/arm64/boot/dts/qcom/sm8750-mtp.dtb: domain-idle-states: cluster-sleep-0:compatible:0: 'domain-idle-state' was expected
> from schema $id: http://devicetree.org/schemas/power/domain-idle-state.yaml#
> arch/arm64/boot/dts/qcom/sm8750-qrd.dtb: domain-idle-states: cluster-sleep-0: 'idle-state-name' does not match any of the regexes: 'pinctrl-[0-9]+'
> from schema $id: http://devicetree.org/schemas/power/domain-idle-state.yaml#
> arch/arm64/boot/dts/qcom/sm8750-qrd.dtb: domain-idle-states: cluster-sleep-0:compatible:0: 'domain-idle-state' was expected
> from schema $id: http://devicetree.org/schemas/power/domain-idle-state.yaml#
These were recently dropped across the board, please drop them
here as well.
> arch/arm64/boot/dts/qcom/sm8750-mtp.dtb: pmic@7: 'eusb2-repeater@fd00' does not match any of the regexes: '(.*)?(wled|leds)@[0-9a-f]+$', '^adc-tm@[0-9a-f]+$', '^adc@[0-9a-f]+$', '^audio-codec@[0-9a-f]+$', '^battery@[0-9a-f]+$', '^charger@[0-9a-f]+$', '^led-controller@[0-9a-f]+$', '^mpps@[0-9a-f]+$', '^nvram@[0-9a-f]+$', '^pbs@[0-9a-f]+$', '^rtc@[0-9a-f]+$', '^temp-alarm@[0-9a-f]+$', '^typec@[0-9a-f]+$', '^usb-detect@[0-9a-f]+$', '^usb-vbus-regulator@[0-9a-f]+$', '^vibrator@[0-9a-f]+$', 'gpio@[0-9a-f]+$', 'phy@[0-9a-f]+$', 'pinctrl-[0-9]+', 'pon@[0-9a-f]+$'
> from schema $id: http://devicetree.org/schemas/mfd/qcom,spmi-pmic.yaml#
> arch/arm64/boot/dts/qcom/sm8750-qrd.dtb: pmic@7: 'eusb2-repeater@fd00' does not match any of the regexes: '(.*)?(wled|leds)@[0-9a-f]+$', '^adc-tm@[0-9a-f]+$', '^adc@[0-9a-f]+$', '^audio-codec@[0-9a-f]+$', '^battery@[0-9a-f]+$', '^charger@[0-9a-f]+$', '^led-controller@[0-9a-f]+$', '^mpps@[0-9a-f]+$', '^nvram@[0-9a-f]+$', '^pbs@[0-9a-f]+$', '^rtc@[0-9a-f]+$', '^temp-alarm@[0-9a-f]+$', '^typec@[0-9a-f]+$', '^usb-detect@[0-9a-f]+$', '^usb-vbus-regulator@[0-9a-f]+$', '^vibrator@[0-9a-f]+$', 'gpio@[0-9a-f]+$', 'phy@[0-9a-f]+$', 'pinctrl-[0-9]+', 'pon@[0-9a-f]+$'
phy@ (as seen in x1e80100-pmics.dtsi)
> from schema $id: http://devicetree.org/schemas/mfd/qcom,spmi-pmic.yaml#
> arch/arm64/boot/dts/qcom/sm8750-mtp.dtb: rsc@16500000: regulators-0: Unevaluated properties are not allowed ('vdd-l1-supply', 'vdd-l10-supply', 'vdd-l4-supply' were unexpected)
> from schema $id: http://devicetree.org/schemas/soc/qcom/qcom,rpmh-rsc.yaml#
> arch/arm64/boot/dts/qcom/sm8750-mtp.dtb: rsc@16500000: regulators-0: Unevaluated properties are not allowed ('vdd-l1-supply', 'vdd-l10-supply', 'vdd-l4-supply' were unexpected)
> from schema $id: http://devicetree.org/schemas/soc/qcom/qcom,rpmh-rsc.yaml#
> arch/arm64/boot/dts/qcom/sm8750-mtp.dtb: rsc@16500000: regulators-4: Unevaluated properties are not allowed ('vdd-s7-supply', 'vdd-s8-supply' were unexpected)
> from schema $id: http://devicetree.org/schemas/soc/qcom/qcom,rpmh-rsc.yaml#
> arch/arm64/boot/dts/qcom/sm8750-mtp.dtb: rsc@16500000: regulators-4: Unevaluated properties are not allowed ('vdd-s7-supply', 'vdd-s8-supply' were unexpected)
> from schema $id: http://devicetree.org/schemas/soc/qcom/qcom,rpmh-rsc.yaml#
These need bindings updates
> arch/arm64/boot/dts/qcom/sm8750-mtp.dtb: rsc@16500000: 'power-domains' is a required property
> from schema $id: http://devicetree.org/schemas/soc/qcom/qcom,rpmh-rsc.yaml#
This I'll address when reviewing the dt
[...] (skipping a bunch of duplicates)
> arch/arm64/boot/dts/qcom/sm8750-mtp.dtb: timer@16800000: #size-cells: 1 was expected
> from schema $id: http://devicetree.org/schemas/timer/arm,arch_timer_mmio.yaml#
> arch/arm64/boot/dts/qcom/sm8750-qrd.dtb: timer@16800000: #size-cells: 1 was expected
> from schema $id: http://devicetree.org/schemas/timer/arm,arch_timer_mmio.yaml#
#address-cells <2> is fine, #size-cells must be 1, apparently
Konrad
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 0/5] dts: qcom: Introduce SM8750 device trees
2024-10-24 17:22 ` Konrad Dybcio
@ 2024-10-24 22:46 ` Melody Olvera
2024-11-02 9:36 ` Konrad Dybcio
0 siblings, 1 reply; 18+ messages in thread
From: Melody Olvera @ 2024-10-24 22:46 UTC (permalink / raw)
To: Konrad Dybcio, Rob Herring (Arm)
Cc: Arnd Bergmann, Dmitry Baryshkov, Nícolas F . R . A . Prado,
linux-arm-kernel, devicetree, linux-kernel,
Satya Durga Srinivasu Prabhala, Trilok Soni,
AngeloGioacchino Del Regno, Neil Armstrong, Lee Jones,
Konrad Dybcio, Conor Dooley, Stephen Boyd, Krzysztof Kozlowski,
Bjorn Andersson, linux-arm-msm, Catalin Marinas,
Geert Uytterhoeven, Will Deacon
On 10/24/2024 10:22 AM, Konrad Dybcio wrote:
> On 24.10.2024 6:33 PM, Rob Herring (Arm) wrote:
>> On Mon, 21 Oct 2024 16:21:09 -0700, Melody Olvera wrote:
>>> This series adds the initial device tree support for the SM8750 SoCs
>>> needed to boot to shell. This specifically adds support for clocks,
>>> pinctrl, rpmhpd, regulators, interconnects, and SoC and board
>>> compatibles.
>>>
> [...]
>
>> New warnings running 'make CHECK_DTBS=y qcom/sm8750-mtp.dtb qcom/sm8750-qrd.dtb' for 20241021232114.2636083-1-quic_molvera@quicinc.com:
>>
>> arch/arm64/boot/dts/qcom/sm8750-mtp.dtb: domain-idle-states: cluster-sleep-0: 'idle-state-name' does not match any of the regexes: 'pinctrl-[0-9]+'
>> from schema $id: http://devicetree.org/schemas/power/domain-idle-state.yaml#
>> arch/arm64/boot/dts/qcom/sm8750-mtp.dtb: domain-idle-states: cluster-sleep-0:compatible:0: 'domain-idle-state' was expected
>> from schema $id: http://devicetree.org/schemas/power/domain-idle-state.yaml#
>> arch/arm64/boot/dts/qcom/sm8750-qrd.dtb: domain-idle-states: cluster-sleep-0: 'idle-state-name' does not match any of the regexes: 'pinctrl-[0-9]+'
>> from schema $id: http://devicetree.org/schemas/power/domain-idle-state.yaml#
>> arch/arm64/boot/dts/qcom/sm8750-qrd.dtb: domain-idle-states: cluster-sleep-0:compatible:0: 'domain-idle-state' was expected
>> from schema $id: http://devicetree.org/schemas/power/domain-idle-state.yaml#
> These were recently dropped across the board, please drop them
> here as well.
Ack.
>
>> arch/arm64/boot/dts/qcom/sm8750-mtp.dtb: pmic@7: 'eusb2-repeater@fd00' does not match any of the regexes: '(.*)?(wled|leds)@[0-9a-f]+$', '^adc-tm@[0-9a-f]+$', '^adc@[0-9a-f]+$', '^audio-codec@[0-9a-f]+$', '^battery@[0-9a-f]+$', '^charger@[0-9a-f]+$', '^led-controller@[0-9a-f]+$', '^mpps@[0-9a-f]+$', '^nvram@[0-9a-f]+$', '^pbs@[0-9a-f]+$', '^rtc@[0-9a-f]+$', '^temp-alarm@[0-9a-f]+$', '^typec@[0-9a-f]+$', '^usb-detect@[0-9a-f]+$', '^usb-vbus-regulator@[0-9a-f]+$', '^vibrator@[0-9a-f]+$', 'gpio@[0-9a-f]+$', 'phy@[0-9a-f]+$', 'pinctrl-[0-9]+', 'pon@[0-9a-f]+$'
>> from schema $id: http://devicetree.org/schemas/mfd/qcom,spmi-pmic.yaml#
>> arch/arm64/boot/dts/qcom/sm8750-qrd.dtb: pmic@7: 'eusb2-repeater@fd00' does not match any of the regexes: '(.*)?(wled|leds)@[0-9a-f]+$', '^adc-tm@[0-9a-f]+$', '^adc@[0-9a-f]+$', '^audio-codec@[0-9a-f]+$', '^battery@[0-9a-f]+$', '^charger@[0-9a-f]+$', '^led-controller@[0-9a-f]+$', '^mpps@[0-9a-f]+$', '^nvram@[0-9a-f]+$', '^pbs@[0-9a-f]+$', '^rtc@[0-9a-f]+$', '^temp-alarm@[0-9a-f]+$', '^typec@[0-9a-f]+$', '^usb-detect@[0-9a-f]+$', '^usb-vbus-regulator@[0-9a-f]+$', '^vibrator@[0-9a-f]+$', 'gpio@[0-9a-f]+$', 'phy@[0-9a-f]+$', 'pinctrl-[0-9]+', 'pon@[0-9a-f]+$'
> phy@ (as seen in x1e80100-pmics.dtsi)
Ack.
>
>> from schema $id: http://devicetree.org/schemas/mfd/qcom,spmi-pmic.yaml#
>> arch/arm64/boot/dts/qcom/sm8750-mtp.dtb: rsc@16500000: regulators-0: Unevaluated properties are not allowed ('vdd-l1-supply', 'vdd-l10-supply', 'vdd-l4-supply' were unexpected)
>> from schema $id: http://devicetree.org/schemas/soc/qcom/qcom,rpmh-rsc.yaml#
>> arch/arm64/boot/dts/qcom/sm8750-mtp.dtb: rsc@16500000: regulators-0: Unevaluated properties are not allowed ('vdd-l1-supply', 'vdd-l10-supply', 'vdd-l4-supply' were unexpected)
These actually needed to be combined; they should be
vdd-l1-l4-l10-supply. Will fix.
>> from schema $id: http://devicetree.org/schemas/soc/qcom/qcom,rpmh-rsc.yaml#
>> arch/arm64/boot/dts/qcom/sm8750-mtp.dtb: rsc@16500000: regulators-4: Unevaluated properties are not allowed ('vdd-s7-supply', 'vdd-s8-supply' were unexpected)
>> from schema $id: http://devicetree.org/schemas/soc/qcom/qcom,rpmh-rsc.yaml#
>> arch/arm64/boot/dts/qcom/sm8750-mtp.dtb: rsc@16500000: regulators-4: Unevaluated properties are not allowed ('vdd-s7-supply', 'vdd-s8-supply' were unexpected)
>> from schema $id: http://devicetree.org/schemas/soc/qcom/qcom,rpmh-rsc.yaml#
> These need bindings updates
Agreed; this regulator is not documented correctly. Will address in a v2 ps.
>
>> arch/arm64/boot/dts/qcom/sm8750-mtp.dtb: rsc@16500000: 'power-domains' is a required property
>> from schema $id: http://devicetree.org/schemas/soc/qcom/qcom,rpmh-rsc.yaml#
> This I'll address when reviewing the dt
So for this, let me know if the following seems about right.
The rsc node needs a system-wide power domain defined. To accomplish
this, I would define
a system_pd node and point both cluster pd nodes to it via
power-domains, similar to what you did here:
https://lore.kernel.org/all/20240102-topic-x1e_fixes-v1-3-70723e08d5f6@linaro.org/
Then, extrapolating from that, I can define a system-wide idle-state
under the domain-idle-state node as follows:
domain_ss3: domain-sleep-0 {
compatible = "domain-idle-state";
[...] (omitting a bunch of details, but you get the point)
};
And then point to that from the new system_pd node under the psci node:
system_pd: power-domain-system {
#power-domain-cells = <0>;
domain-idle-states = <&domain_ss3>;
};
And then of course in the rsc node, have power-domains = <&system_pd>;
Is that correct?
>
> [...] (skipping a bunch of duplicates)
>
>> arch/arm64/boot/dts/qcom/sm8750-mtp.dtb: timer@16800000: #size-cells: 1 was expected
>> from schema $id: http://devicetree.org/schemas/timer/arm,arch_timer_mmio.yaml#
>> arch/arm64/boot/dts/qcom/sm8750-qrd.dtb: timer@16800000: #size-cells: 1 was expected
>> from schema $id: http://devicetree.org/schemas/timer/arm,arch_timer_mmio.yaml#
> #address-cells <2> is fine, #size-cells must be 1, apparently
Ack.
Thanks,
Melody
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: (subset) [PATCH 2/5] dt-bindings: mfd: qcom,spmi-pmic: Document PMICs added in SM8750
2024-10-21 23:21 ` [PATCH 2/5] dt-bindings: mfd: qcom,spmi-pmic: Document PMICs added in SM8750 Melody Olvera
2024-10-23 8:30 ` Krzysztof Kozlowski
@ 2024-11-01 15:56 ` Lee Jones
1 sibling, 0 replies; 18+ messages in thread
From: Lee Jones @ 2024-11-01 15:56 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Lee Jones, Catalin Marinas, Will Deacon,
Geert Uytterhoeven, Dmitry Baryshkov, AngeloGioacchino Del Regno,
Neil Armstrong, Arnd Bergmann, Nícolas F . R . A . Prado,
Stephen Boyd, Trilok Soni, Satya Durga Srinivasu Prabhala,
Melody Olvera
Cc: linux-arm-msm, devicetree, linux-kernel, linux-arm-kernel,
Jishnu Prakash
On Mon, 21 Oct 2024 16:21:11 -0700, Melody Olvera wrote:
> Document compatibles for the added pmd8028 and pmih0108 SPMI PMICs.
>
>
Applied, thanks!
[2/5] dt-bindings: mfd: qcom,spmi-pmic: Document PMICs added in SM8750
commit: 42e34f8446252a3dde70822d7e6f8d7d86ec20f4
--
Lee Jones [李琼斯]
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 4/5] arm64: dts: qcom: Add base sm8750 dtsi and mtp and qrd dts
2024-10-21 23:21 ` [PATCH 4/5] arm64: dts: qcom: Add base sm8750 dtsi and mtp and qrd dts Melody Olvera
2024-10-23 3:12 ` Bjorn Andersson
@ 2024-11-02 9:36 ` Konrad Dybcio
2024-11-04 22:18 ` Melody Olvera
1 sibling, 1 reply; 18+ messages in thread
From: Konrad Dybcio @ 2024-11-02 9:36 UTC (permalink / raw)
To: Melody Olvera, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Lee Jones, Catalin Marinas,
Will Deacon, Geert Uytterhoeven, Dmitry Baryshkov,
AngeloGioacchino Del Regno, Neil Armstrong, Arnd Bergmann,
Nícolas F . R . A . Prado, Stephen Boyd, Trilok Soni,
Satya Durga Srinivasu Prabhala
Cc: linux-arm-msm, devicetree, linux-kernel, linux-arm-kernel,
Taniya Das, Jishnu Prakash, Raviteja Laggyshetty
On 22.10.2024 1:21 AM, Melody Olvera wrote:
> Add base dtsi for the sm8750 SoC describing the CPUs, GCC and
> RPMHCC clock controllers, geni UART, interrupt controller, TLMM,
> reserved memory, interconnects, regulator, and SMMU nodes. Also add
> MTP and QRD board dts files for sm8750.
>
> Co-developed-by: Taniya Das <quic_tdas@quicinc.com>
> Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
> Co-developed-by: Jishnu Prakash <quic_jprakash@quicinc.com>
> Signed-off-by: Jishnu Prakash <quic_jprakash@quicinc.com>
> Co-developed-by: Raviteja Laggyshetty <quic_rlaggysh@quicinc.com>
> Signed-off-by: Raviteja Laggyshetty <quic_rlaggysh@quicinc.com>
> Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
> ---
[...]
> +&spmi_bus {
> + pm8550ve_d: pmic@3 {
These usually go to a separate file each.. But I see why that would
be difficult here.
Lately I've been a fan of <socname>-pmics.dtsi. WDYT, Bjorn?
[...]
> + apps_smmu: iommu@15000000 {
> + compatible = "qcom,sm8750-smmu-500", "qcom,smmu-500", "arm,mmu-500";
> + reg = <0x0 0x15000000 0x0 0x100000>;
> +
[...]
> + #iommu-cells = <2>;
> + #global-interrupts = <1>;
This is usually dma-coherent, you can determine that through a smoke
test
> + };
> +
> + intc: interrupt-controller@16000000 {
> + compatible = "arm,gic-v3";
> + reg = <0x0 0x16000000 0x0 0x10000>, /* GICD */
> + <0x0 0x16080000 0x0 0x200000>; /* GICR * 12 */
These comments are copypasted gen to gen and don't bring much
information atop what's in bindings
Konrad
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 0/5] dts: qcom: Introduce SM8750 device trees
2024-10-24 22:46 ` Melody Olvera
@ 2024-11-02 9:36 ` Konrad Dybcio
0 siblings, 0 replies; 18+ messages in thread
From: Konrad Dybcio @ 2024-11-02 9:36 UTC (permalink / raw)
To: Melody Olvera, Konrad Dybcio, Rob Herring (Arm)
Cc: Arnd Bergmann, Dmitry Baryshkov, Nícolas F . R . A . Prado,
linux-arm-kernel, devicetree, linux-kernel,
Satya Durga Srinivasu Prabhala, Trilok Soni,
AngeloGioacchino Del Regno, Neil Armstrong, Lee Jones,
Konrad Dybcio, Conor Dooley, Stephen Boyd, Krzysztof Kozlowski,
Bjorn Andersson, linux-arm-msm, Catalin Marinas,
Geert Uytterhoeven, Will Deacon
On 25.10.2024 12:46 AM, Melody Olvera wrote:
>
>
> On 10/24/2024 10:22 AM, Konrad Dybcio wrote:
>> On 24.10.2024 6:33 PM, Rob Herring (Arm) wrote:
>>> On Mon, 21 Oct 2024 16:21:09 -0700, Melody Olvera wrote:
>>>> This series adds the initial device tree support for the SM8750 SoCs
>>>> needed to boot to shell. This specifically adds support for clocks,
>>>> pinctrl, rpmhpd, regulators, interconnects, and SoC and board
>>>> compatibles.
[...]
>>> arch/arm64/boot/dts/qcom/sm8750-mtp.dtb: rsc@16500000: 'power-domains' is a required property
>>> from schema $id: http://devicetree.org/schemas/soc/qcom/qcom,rpmh-rsc.yaml#
>> This I'll address when reviewing the dt
>
> So for this, let me know if the following seems about right.
> The rsc node needs a system-wide power domain defined. To accomplish this, I would define
> a system_pd node and point both cluster pd nodes to it via power-domains, similar to what you did here:
> https://lore.kernel.org/all/20240102-topic-x1e_fixes-v1-3-70723e08d5f6@linaro.org/
>
> Then, extrapolating from that, I can define a system-wide idle-state under the domain-idle-state node as follows:
> domain_ss3: domain-sleep-0 {
> compatible = "domain-idle-state";
> [...] (omitting a bunch of details, but you get the point)
> };
>
> And then point to that from the new system_pd node under the psci node:
> system_pd: power-domain-system {
> #power-domain-cells = <0>;
> domain-idle-states = <&domain_ss3>;
> };
>
> And then of course in the rsc node, have power-domains = <&system_pd>;
>
> Is that correct?
Yes, please go ahead with this
Konrad
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 4/5] arm64: dts: qcom: Add base sm8750 dtsi and mtp and qrd dts
2024-11-02 9:36 ` Konrad Dybcio
@ 2024-11-04 22:18 ` Melody Olvera
0 siblings, 0 replies; 18+ messages in thread
From: Melody Olvera @ 2024-11-04 22:18 UTC (permalink / raw)
To: Konrad Dybcio, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Lee Jones, Catalin Marinas,
Will Deacon, Geert Uytterhoeven, Dmitry Baryshkov,
AngeloGioacchino Del Regno, Neil Armstrong, Arnd Bergmann,
Nícolas F . R . A . Prado, Stephen Boyd, Trilok Soni,
Satya Durga Srinivasu Prabhala
Cc: linux-arm-msm, devicetree, linux-kernel, linux-arm-kernel,
Taniya Das, Jishnu Prakash, Raviteja Laggyshetty
On 11/2/2024 2:36 AM, Konrad Dybcio wrote:
> On 22.10.2024 1:21 AM, Melody Olvera wrote:
>> Add base dtsi for the sm8750 SoC describing the CPUs, GCC and
>> RPMHCC clock controllers, geni UART, interrupt controller, TLMM,
>> reserved memory, interconnects, regulator, and SMMU nodes. Also add
>> MTP and QRD board dts files for sm8750.
>>
>> Co-developed-by: Taniya Das <quic_tdas@quicinc.com>
>> Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
>> Co-developed-by: Jishnu Prakash <quic_jprakash@quicinc.com>
>> Signed-off-by: Jishnu Prakash <quic_jprakash@quicinc.com>
>> Co-developed-by: Raviteja Laggyshetty <quic_rlaggysh@quicinc.com>
>> Signed-off-by: Raviteja Laggyshetty <quic_rlaggysh@quicinc.com>
>> Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
>> ---
> [...]
>
>> +&spmi_bus {
>> + pm8550ve_d: pmic@3 {
> These usually go to a separate file each.. But I see why that would
> be difficult here.
>
> Lately I've been a fan of <socname>-pmics.dtsi. WDYT, Bjorn?
SGTM, if Bjorn is fine w it, I can make that change; I'll do it similar
to x1e80100-pmics.dtsi.
>
> [...]
>
>> + apps_smmu: iommu@15000000 {
>> + compatible = "qcom,sm8750-smmu-500", "qcom,smmu-500", "arm,mmu-500";
>> + reg = <0x0 0x15000000 0x0 0x100000>;
>> +
> [...]
>
>> + #iommu-cells = <2>;
>> + #global-interrupts = <1>;
> This is usually dma-coherent, you can determine that through a smoke
> test
Ah yes good catch; this is supposed to be dma-coherent. Will add.
>
>> + };
>> +
>> + intc: interrupt-controller@16000000 {
>> + compatible = "arm,gic-v3";
>> + reg = <0x0 0x16000000 0x0 0x10000>, /* GICD */
>> + <0x0 0x16080000 0x0 0x200000>; /* GICR * 12 */
> These comments are copypasted gen to gen and don't bring much
> information atop what's in bindings
>
Ack. Will remove.
Thanks,
Melody
^ permalink raw reply [flat|nested] 18+ messages in thread
end of thread, other threads:[~2024-11-04 22:18 UTC | newest]
Thread overview: 18+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2024-10-21 23:21 [PATCH 0/5] dts: qcom: Introduce SM8750 device trees Melody Olvera
2024-10-21 23:21 ` [PATCH 1/5] dt-bindings: arm: qcom: Document sm8750 SoC and boards Melody Olvera
2024-10-23 8:29 ` Krzysztof Kozlowski
2024-10-21 23:21 ` [PATCH 2/5] dt-bindings: mfd: qcom,spmi-pmic: Document PMICs added in SM8750 Melody Olvera
2024-10-23 8:30 ` Krzysztof Kozlowski
2024-11-01 15:56 ` (subset) " Lee Jones
2024-10-21 23:21 ` [PATCH 3/5] arm64: dts: qcom: Add pmd8028 and pmih0108 PMIC dtsi files Melody Olvera
2024-10-21 23:21 ` [PATCH 4/5] arm64: dts: qcom: Add base sm8750 dtsi and mtp and qrd dts Melody Olvera
2024-10-23 3:12 ` Bjorn Andersson
2024-10-23 21:58 ` Melody Olvera
2024-11-02 9:36 ` Konrad Dybcio
2024-11-04 22:18 ` Melody Olvera
2024-10-21 23:21 ` [PATCH 5/5] arm64: defconfig: Enable SM8750 SoC base configs Melody Olvera
2024-10-23 8:31 ` Krzysztof Kozlowski
2024-10-24 16:33 ` [PATCH 0/5] dts: qcom: Introduce SM8750 device trees Rob Herring (Arm)
2024-10-24 17:22 ` Konrad Dybcio
2024-10-24 22:46 ` Melody Olvera
2024-11-02 9:36 ` Konrad Dybcio
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