[PATCH v4 0/3] riscv: interrupt-controller: Add T-HEAD C900 ACLINT SSWI

devicetree.vger.kernel.org archive mirror
 help / color / mirror / Atom feed

* [PATCH v4 0/3] riscv: interrupt-controller: Add T-HEAD C900 ACLINT SSWI
@ 2024-10-22  4:02 Inochi Amaoto
  2024-10-22  4:02 ` [PATCH v4 1/3] dt-bindings: interrupt-controller: Add Sophgo SG2044 " Inochi Amaoto
                   ` (2 more replies)
  0 siblings, 3 replies; 7+ messages in thread
From: Inochi Amaoto @ 2024-10-22  4:02 UTC (permalink / raw)
  To: Chen Wang, Thomas Gleixner, Rob Herring, Krzysztof Kozlowski,
	Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou,
	Peter Zijlstra, Inochi Amaoto, Geert Uytterhoeven, Lad Prabhakar,
	Yangyu Chen, Hal Feng
  Cc: Yixun Lan, Inochi Amaoto, linux-kernel, devicetree, linux-riscv

New version of T-HEAD C920 implement a fully featured ACLINT[1] device
(This core is used by Sophgo SG2044). This ACLINT device provides a
SSWI field to support fast S-mode IPI. This SSWI device is like the
MSWI device in CLINT/ACLINT, but for S-mode. The only thing is different
from the draft is that the T-HEAD version SSWI needs to write 0 on the
SSWI address to clear the IPI.

Add full support for T-HEAD C900 SSWI device.

[1] https://github.com/riscv/riscv-aclint

Changed from v1:
1. patch 2: use computed reg offset to avoid uncessary reg additions
   when setting/clearing irq.
2. patch 2: fix mulitple format issues and improve some comments.
3. patch 2: disable cpu irq when CPU is stopped.

Changed from v2:
1. patch 2: add SXSTATUS.CLINTEE check for T-HEAD cores.
2. patch 2: add select GENERIC_IRQ_IPI_MUX in Kconfig

Changed from v3:
2. patch 2: add SMP depends in Kconfig

Inochi Amaoto (3):
  dt-bindings: interrupt-controller: Add Sophgo SG2044 ACLINT SSWI
  irqchip: add T-HEAD C900 ACLINT SSWI driver
  riscv: defconfig: Enable T-HEAD C900 ACLINT SSWI drivers

 .../thead,c900-aclint-sswi.yaml               |  58 ++++++
 arch/riscv/configs/defconfig                  |   1 +
 drivers/irqchip/Kconfig                       |  12 ++
 drivers/irqchip/Makefile                      |   1 +
 drivers/irqchip/irq-thead-c900-aclint-sswi.c  | 176 ++++++++++++++++++
 include/linux/cpuhotplug.h                    |   1 +
 6 files changed, 249 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-sswi.yaml
 create mode 100644 drivers/irqchip/irq-thead-c900-aclint-sswi.c

--
2.47.0

^ permalink raw reply	[flat|nested] 7+ messages in thread

* [PATCH v4 1/3] dt-bindings: interrupt-controller: Add Sophgo SG2044 ACLINT SSWI
  2024-10-22  4:02 [PATCH v4 0/3] riscv: interrupt-controller: Add T-HEAD C900 ACLINT SSWI Inochi Amaoto
@ 2024-10-22  4:02 ` Inochi Amaoto
  2024-10-22  4:02 ` [PATCH v4 2/3] irqchip: add T-HEAD C900 ACLINT SSWI driver Inochi Amaoto
  2024-10-22  4:02 ` [PATCH v4 3/3] riscv: defconfig: Enable T-HEAD C900 ACLINT SSWI drivers Inochi Amaoto
  2 siblings, 0 replies; 7+ messages in thread
From: Inochi Amaoto @ 2024-10-22  4:02 UTC (permalink / raw)
  To: Chen Wang, Thomas Gleixner, Rob Herring, Krzysztof Kozlowski,
	Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou,
	Peter Zijlstra, Inochi Amaoto, Geert Uytterhoeven, Lad Prabhakar,
	Yangyu Chen, Hal Feng
  Cc: Yixun Lan, Inochi Amaoto, linux-kernel, devicetree, linux-riscv,
	Conor Dooley

Sophgo SG2044 has a new version of T-HEAD C920, which implement
a fully featured ACLINT device. This ACLINT has an extra SSWI
field to support fast S-mode IPI.

Add necessary compatible string for the T-HEAD ACLINT sswi device.

Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
---
 .../thead,c900-aclint-sswi.yaml               | 58 +++++++++++++++++++
 1 file changed, 58 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-sswi.yaml

diff --git a/Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-sswi.yaml b/Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-sswi.yaml
new file mode 100644
index 000000000000..0106fbf3ea1f
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-sswi.yaml
@@ -0,0 +1,58 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interrupt-controller/thead,c900-aclint-sswi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Sophgo sg2044 ACLINT Supervisor-level Software Interrupt Device
+
+maintainers:
+  - Inochi Amaoto <inochiama@outlook.com>
+
+description:
+  The SSWI device is a part of the riscv ACLINT device. It provides
+  supervisor-level IPI functionality for a set of HARTs on a RISC-V
+  platform. It provides a register to set an IPI (SETSSIP) for each
+  HART connected to the SSWI device.
+
+properties:
+  compatible:
+    items:
+      - enum:
+          - sophgo,sg2044-aclint-sswi
+      - const: thead,c900-aclint-sswi
+
+  reg:
+    maxItems: 1
+
+  "#interrupt-cells":
+    const: 0
+
+  interrupt-controller: true
+
+  interrupts-extended:
+    minItems: 1
+    maxItems: 4095
+
+additionalProperties: false
+
+required:
+  - compatible
+  - reg
+  - "#interrupt-cells"
+  - interrupt-controller
+  - interrupts-extended
+
+examples:
+  - |
+    interrupt-controller@94000000 {
+      compatible = "sophgo,sg2044-aclint-sswi", "thead,c900-aclint-sswi";
+      reg = <0x94000000 0x00004000>;
+      #interrupt-cells = <0>;
+      interrupt-controller;
+      interrupts-extended = <&cpu1intc 1>,
+                            <&cpu2intc 1>,
+                            <&cpu3intc 1>,
+                            <&cpu4intc 1>;
+    };
+...
-- 
2.47.0


^ permalink raw reply related	[flat|nested] 7+ messages in thread

* [PATCH v4 2/3] irqchip: add T-HEAD C900 ACLINT SSWI driver
  2024-10-22  4:02 [PATCH v4 0/3] riscv: interrupt-controller: Add T-HEAD C900 ACLINT SSWI Inochi Amaoto
  2024-10-22  4:02 ` [PATCH v4 1/3] dt-bindings: interrupt-controller: Add Sophgo SG2044 " Inochi Amaoto
@ 2024-10-22  4:02 ` Inochi Amaoto
  2024-10-29  7:45   ` Thomas Gleixner
  2024-10-22  4:02 ` [PATCH v4 3/3] riscv: defconfig: Enable T-HEAD C900 ACLINT SSWI drivers Inochi Amaoto
  2 siblings, 1 reply; 7+ messages in thread
From: Inochi Amaoto @ 2024-10-22  4:02 UTC (permalink / raw)
  To: Chen Wang, Thomas Gleixner, Rob Herring, Krzysztof Kozlowski,
	Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou,
	Peter Zijlstra, Inochi Amaoto, Geert Uytterhoeven, Lad Prabhakar,
	Yangyu Chen, Hal Feng
  Cc: Yixun Lan, Inochi Amaoto, linux-kernel, devicetree, linux-riscv

Add a driver for the T-HEAD C900 ACLINT SSWI device, which is an
enhanced implementation of the RISC-V ACLINT SSWI specification.
This device allows the system to send ipi via fast device interface.

Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
---
 drivers/irqchip/Kconfig                      |  12 ++
 drivers/irqchip/Makefile                     |   1 +
 drivers/irqchip/irq-thead-c900-aclint-sswi.c | 176 +++++++++++++++++++
 include/linux/cpuhotplug.h                   |   1 +
 4 files changed, 190 insertions(+)
 create mode 100644 drivers/irqchip/irq-thead-c900-aclint-sswi.c

diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index 341cd9ca5a05..b6e8411f28d3 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -611,6 +611,18 @@ config STARFIVE_JH8100_INTC
 
 	  If you don't know what to do here, say Y.
 
+config THEAD_C900_ACLINT_SSWI
+	bool "THEAD C9XX ACLINT S-mode IPI Interrupt Controller"
+	depends on RISCV
+	depends on SMP
+	select IRQ_DOMAIN_HIERARCHY
+	select GENERIC_IRQ_IPI_MUX
+	help
+	  This enables support for T-HEAD specific ACLINT SSWI device
+	  support.
+
+	  If you don't know what to do here, say Y.
+
 config EXYNOS_IRQ_COMBINER
 	bool "Samsung Exynos IRQ combiner support" if COMPILE_TEST
 	depends on (ARCH_EXYNOS && ARM) || COMPILE_TEST
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index e3679ec2b9f7..583418261253 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -101,6 +101,7 @@ obj-$(CONFIG_RISCV_APLIC_MSI)		+= irq-riscv-aplic-msi.o
 obj-$(CONFIG_RISCV_IMSIC)		+= irq-riscv-imsic-state.o irq-riscv-imsic-early.o irq-riscv-imsic-platform.o
 obj-$(CONFIG_SIFIVE_PLIC)		+= irq-sifive-plic.o
 obj-$(CONFIG_STARFIVE_JH8100_INTC)	+= irq-starfive-jh8100-intc.o
+obj-$(CONFIG_THEAD_C900_ACLINT_SSWI)	+= irq-thead-c900-aclint-sswi.o
 obj-$(CONFIG_IMX_IRQSTEER)		+= irq-imx-irqsteer.o
 obj-$(CONFIG_IMX_INTMUX)		+= irq-imx-intmux.o
 obj-$(CONFIG_IMX_MU_MSI)		+= irq-imx-mu-msi.o
diff --git a/drivers/irqchip/irq-thead-c900-aclint-sswi.c b/drivers/irqchip/irq-thead-c900-aclint-sswi.c
new file mode 100644
index 000000000000..e1051869a7ab
--- /dev/null
+++ b/drivers/irqchip/irq-thead-c900-aclint-sswi.c
@@ -0,0 +1,176 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2024 Inochi Amaoto <inochiama@gmail.com>
+ */
+
+#define pr_fmt(fmt) "thead-c900-aclint-sswi: " fmt
+#include <linux/cpu.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/irqchip.h>
+#include <linux/irqchip/chained_irq.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/pci.h>
+#include <linux/spinlock.h>
+#include <linux/smp.h>
+#include <linux/string_choices.h>
+#include <asm/sbi.h>
+#include <asm/vendorid_list.h>
+
+#define ACLINT_xSWI_REGISTER_SIZE	4
+
+#define THEAD_C9XX_CSR_SXSTATUS		0x5c0
+#define THEAD_C9XX_SXSTATUS_CLINTEE	BIT(17)
+
+static int sswi_ipi_virq __ro_after_init;
+static DEFINE_PER_CPU(void __iomem *, sswi_cpu_regs);
+
+static void thead_aclint_sswi_ipi_send(unsigned int cpu)
+{
+	writel_relaxed(0x1, per_cpu(sswi_cpu_regs, cpu));
+}
+
+static void thead_aclint_sswi_ipi_clear(void)
+{
+	writel_relaxed(0x0, this_cpu_read(sswi_cpu_regs));
+}
+
+static void thead_aclint_sswi_ipi_handle(struct irq_desc *desc)
+{
+	struct irq_chip *chip = irq_desc_get_chip(desc);
+
+	chained_irq_enter(chip, desc);
+
+	csr_clear(CSR_IP, IE_SIE);
+	thead_aclint_sswi_ipi_clear();
+
+	ipi_mux_process();
+
+	chained_irq_exit(chip, desc);
+}
+
+static int thead_aclint_sswi_starting_cpu(unsigned int cpu)
+{
+	enable_percpu_irq(sswi_ipi_virq, irq_get_trigger_type(sswi_ipi_virq));
+
+	return 0;
+}
+
+static int thead_aclint_sswi_dying_cpu(unsigned int cpu)
+{
+	thead_aclint_sswi_ipi_clear();
+
+	disable_percpu_irq(sswi_ipi_virq);
+
+	return 0;
+}
+
+static int __init aclint_sswi_parse_irq(struct fwnode_handle *fwnode,
+					void __iomem *reg)
+{
+	struct of_phandle_args parent;
+	unsigned long hartid;
+	u32 contexts, i;
+	int rc, cpu;
+
+	contexts = of_irq_count(to_of_node(fwnode));
+	if (!(contexts)) {
+		pr_err("%pfwP: no ACLINT SSWI context available\n", fwnode);
+		return -EINVAL;
+	}
+
+	for (i = 0; i < contexts; i++) {
+		rc = of_irq_parse_one(to_of_node(fwnode), i, &parent);
+		if (rc)
+			return rc;
+
+		rc = riscv_of_parent_hartid(parent.np, &hartid);
+		if (rc)
+			return rc;
+
+		if (parent.args[0] != RV_IRQ_SOFT)
+			return -ENOTSUPP;
+
+		cpu = riscv_hartid_to_cpuid(hartid);
+
+		per_cpu(sswi_cpu_regs, cpu) = reg + i * ACLINT_xSWI_REGISTER_SIZE;
+	}
+
+	pr_info("%pfwP: register %u CPU%s\n", fwnode, contexts, str_plural(contexts));
+
+	return 0;
+}
+
+static int __init aclint_sswi_probe(struct fwnode_handle *fwnode)
+{
+	struct irq_domain *domain;
+	void __iomem *reg;
+	int virq, rc;
+
+	/* If it is T-HEAD CPU, check whether SSWI is enabled */
+	if (riscv_cached_mvendorid(0) == THEAD_VENDOR_ID &&
+	    !(csr_read(THEAD_C9XX_CSR_SXSTATUS) & THEAD_C9XX_SXSTATUS_CLINTEE))
+		return -ENOTSUPP;
+
+	if (!is_of_node(fwnode))
+		return -EINVAL;
+
+	reg = of_iomap(to_of_node(fwnode), 0);
+	if (!reg)
+		return -ENOMEM;
+
+	/* Parse SSWI setting */
+	rc = aclint_sswi_parse_irq(fwnode, reg);
+	if (rc < 0)
+		return rc;
+
+	/* If mulitple SSWI devices are present, do not register irq again */
+	if (sswi_ipi_virq)
+		return 0;
+
+	/* Find riscv intc domain and create IPI irq mapping */
+	domain = irq_find_matching_fwnode(riscv_get_intc_hwnode(), DOMAIN_BUS_ANY);
+	if (!domain) {
+		pr_err("%pfwP: Failed to find INTC domain\n", fwnode);
+		return -ENOENT;
+	}
+
+	sswi_ipi_virq = irq_create_mapping(domain, RV_IRQ_SOFT);
+	if (!sswi_ipi_virq) {
+		pr_err("unable to create ACLINT SSWI IRQ mapping\n");
+		return -ENOMEM;
+	}
+
+	/* Register SSWI irq and handler */
+	virq = ipi_mux_create(BITS_PER_BYTE, thead_aclint_sswi_ipi_send);
+	if (virq <= 0) {
+		pr_err("unable to create muxed IPIs\n");
+		irq_dispose_mapping(sswi_ipi_virq);
+		return virq < 0 ? virq : -ENOMEM;
+	}
+
+	irq_set_chained_handler(sswi_ipi_virq, thead_aclint_sswi_ipi_handle);
+
+	cpuhp_setup_state(CPUHP_AP_IRQ_THEAD_ACLINT_SSWI_STARTING,
+			  "irqchip/thead-aclint-sswi:starting",
+			  thead_aclint_sswi_starting_cpu,
+			  thead_aclint_sswi_dying_cpu);
+
+	riscv_ipi_set_virq_range(virq, BITS_PER_BYTE);
+
+	/* Announce that SSWI is providing IPIs */
+	pr_info("providing IPIs using THEAD ACLINT SSWI\n");
+
+	return 0;
+}
+
+static int __init aclint_sswi_early_probe(struct device_node *node,
+					  struct device_node *parent)
+{
+	return aclint_sswi_probe(&node->fwnode);
+}
+IRQCHIP_DECLARE(thead_aclint_sswi, "thead,c900-aclint-sswi", aclint_sswi_early_probe);
diff --git a/include/linux/cpuhotplug.h b/include/linux/cpuhotplug.h
index 2361ed4d2b15..799052249c7b 100644
--- a/include/linux/cpuhotplug.h
+++ b/include/linux/cpuhotplug.h
@@ -147,6 +147,7 @@ enum cpuhp_state {
 	CPUHP_AP_IRQ_EIOINTC_STARTING,
 	CPUHP_AP_IRQ_AVECINTC_STARTING,
 	CPUHP_AP_IRQ_SIFIVE_PLIC_STARTING,
+	CPUHP_AP_IRQ_THEAD_ACLINT_SSWI_STARTING,
 	CPUHP_AP_IRQ_RISCV_IMSIC_STARTING,
 	CPUHP_AP_IRQ_RISCV_SBI_IPI_STARTING,
 	CPUHP_AP_ARM_MVEBU_COHERENCY,
-- 
2.47.0


^ permalink raw reply related	[flat|nested] 7+ messages in thread

* Re: [PATCH v4 2/3] irqchip: add T-HEAD C900 ACLINT SSWI driver
  2024-10-22  4:02 ` [PATCH v4 2/3] irqchip: add T-HEAD C900 ACLINT SSWI driver Inochi Amaoto
@ 2024-10-29  7:45   ` Thomas Gleixner
  2024-10-31  5:07     ` Anup Patel
  0 siblings, 1 reply; 7+ messages in thread
From: Thomas Gleixner @ 2024-10-29  7:45 UTC (permalink / raw)
  To: Inochi Amaoto, Chen Wang, Rob Herring, Krzysztof Kozlowski,
	Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou,
	Peter Zijlstra, Inochi Amaoto, Geert Uytterhoeven, Lad Prabhakar,
	Yangyu Chen, Hal Feng
  Cc: Yixun Lan, Inochi Amaoto, linux-kernel, devicetree, linux-riscv

On Tue, Oct 22 2024 at 12:02, Inochi Amaoto wrote:
> Add a driver for the T-HEAD C900 ACLINT SSWI device, which is an
> enhanced implementation of the RISC-V ACLINT SSWI specification.
> This device allows the system to send ipi via fast device interface.
>
> Signed-off-by: Inochi Amaoto <inochiama@gmail.com>

Can someone from the RISCV folks please confirm that thtis is good to
go?

Thanks,

        tglx

^ permalink raw reply	[flat|nested] 7+ messages in thread

* Re: [PATCH v4 2/3] irqchip: add T-HEAD C900 ACLINT SSWI driver
  2024-10-29  7:45   ` Thomas Gleixner
@ 2024-10-31  5:07     ` Anup Patel
  2024-10-31  5:45       ` Inochi Amaoto
  0 siblings, 1 reply; 7+ messages in thread
From: Anup Patel @ 2024-10-31  5:07 UTC (permalink / raw)
  To: Thomas Gleixner
  Cc: Inochi Amaoto, Chen Wang, Rob Herring, Krzysztof Kozlowski,
	Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou,
	Peter Zijlstra, Inochi Amaoto, Geert Uytterhoeven, Lad Prabhakar,
	Yangyu Chen, Hal Feng, Yixun Lan, linux-kernel, devicetree,
	linux-riscv

Hi Thomas,

On Tue, Oct 29, 2024 at 1:16 PM Thomas Gleixner <tglx@linutronix.de> wrote:
>
> On Tue, Oct 22 2024 at 12:02, Inochi Amaoto wrote:
> > Add a driver for the T-HEAD C900 ACLINT SSWI device, which is an
> > enhanced implementation of the RISC-V ACLINT SSWI specification.
> > This device allows the system to send ipi via fast device interface.
> >
> > Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
>
> Can someone from the RISCV folks please confirm that thtis is good to
> go?

The T-HEAD C900 ACLINT SSWI is not compliant to any RISC-V specification
so at this point it is a T-HEAD specific device. The RISC-V ACLINT SSWI
specification cited by this driver was never ratified by RISC-V international
in-favor of the ratified RISC-V AIA specification which has a much cleaner
way of doing IPI (as software injected MSIs) implemented by the IMSIC
driver and this also supports IPI virtualization.

Since this is a T-HEAD specific implementation, the description in all
patches of this series should be updated to replace references of the
RISC-V ACLINT SSWI specification with publicly available T-HEAD
documentation. Once, this is done, I think this series can go ahead.

Regards,
Anup

^ permalink raw reply	[flat|nested] 7+ messages in thread

* Re: [PATCH v4 2/3] irqchip: add T-HEAD C900 ACLINT SSWI driver
  2024-10-31  5:07     ` Anup Patel
@ 2024-10-31  5:45       ` Inochi Amaoto
  0 siblings, 0 replies; 7+ messages in thread
From: Inochi Amaoto @ 2024-10-31  5:45 UTC (permalink / raw)
  To: Anup Patel, Thomas Gleixner
  Cc: Inochi Amaoto, Chen Wang, Rob Herring, Krzysztof Kozlowski,
	Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou,
	Peter Zijlstra, Inochi Amaoto, Geert Uytterhoeven, Lad Prabhakar,
	Yangyu Chen, Hal Feng, Yixun Lan, linux-kernel, devicetree,
	linux-riscv

On Thu, Oct 31, 2024 at 10:37:10AM +0530, Anup Patel wrote:
> Hi Thomas,
> 
> On Tue, Oct 29, 2024 at 1:16 PM Thomas Gleixner <tglx@linutronix.de> wrote:
> >
> > On Tue, Oct 22 2024 at 12:02, Inochi Amaoto wrote:
> > > Add a driver for the T-HEAD C900 ACLINT SSWI device, which is an
> > > enhanced implementation of the RISC-V ACLINT SSWI specification.
> > > This device allows the system to send ipi via fast device interface.
> > >
> > > Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
> >
> > Can someone from the RISCV folks please confirm that thtis is good to
> > go?
> 
> The T-HEAD C900 ACLINT SSWI is not compliant to any RISC-V specification
> so at this point it is a T-HEAD specific device. The RISC-V ACLINT SSWI
> specification cited by this driver was never ratified by RISC-V international
> in-favor of the ratified RISC-V AIA specification which has a much cleaner
> way of doing IPI (as software injected MSIs) implemented by the IMSIC
> driver and this also supports IPI virtualization.
> 
> Since this is a T-HEAD specific implementation, the description in all
> patches of this series should be updated to replace references of the
> RISC-V ACLINT SSWI specification with publicly available T-HEAD
> documentation. Once, this is done, I think this series can go ahead.
> 
> Regards,
> Anup

Thanks for your kindly explanation. I will update all the description
about these patch.

Regards,
Inochi

^ permalink raw reply	[flat|nested] 7+ messages in thread

* [PATCH v4 3/3] riscv: defconfig: Enable T-HEAD C900 ACLINT SSWI drivers
  2024-10-22  4:02 [PATCH v4 0/3] riscv: interrupt-controller: Add T-HEAD C900 ACLINT SSWI Inochi Amaoto
  2024-10-22  4:02 ` [PATCH v4 1/3] dt-bindings: interrupt-controller: Add Sophgo SG2044 " Inochi Amaoto
  2024-10-22  4:02 ` [PATCH v4 2/3] irqchip: add T-HEAD C900 ACLINT SSWI driver Inochi Amaoto
@ 2024-10-22  4:02 ` Inochi Amaoto
  2 siblings, 0 replies; 7+ messages in thread
From: Inochi Amaoto @ 2024-10-22  4:02 UTC (permalink / raw)
  To: Chen Wang, Thomas Gleixner, Rob Herring, Krzysztof Kozlowski,
	Conor Dooley, Paul Walmsley, Palmer Dabbelt, Albert Ou,
	Peter Zijlstra, Inochi Amaoto, Geert Uytterhoeven, Lad Prabhakar,
	Yangyu Chen, Hal Feng
  Cc: Yixun Lan, Inochi Amaoto, linux-kernel, devicetree, linux-riscv

Add support for T-HEAD C900 ACLINT SSWI irqchip.

Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
---
 arch/riscv/configs/defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
index 2341393cfac1..5b1d6325df85 100644
--- a/arch/riscv/configs/defconfig
+++ b/arch/riscv/configs/defconfig
@@ -256,6 +256,7 @@ CONFIG_RPMSG_CTRL=y
 CONFIG_RPMSG_VIRTIO=y
 CONFIG_PM_DEVFREQ=y
 CONFIG_IIO=y
+CONFIG_THEAD_C900_ACLINT_SSWI=y
 CONFIG_PHY_SUN4I_USB=m
 CONFIG_PHY_STARFIVE_JH7110_DPHY_RX=m
 CONFIG_PHY_STARFIVE_JH7110_PCIE=m
-- 
2.47.0


^ permalink raw reply related	[flat|nested] 7+ messages in thread

end of thread, other threads:[~2024-10-31  5:45 UTC | newest]

Thread overview: 7+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2024-10-22  4:02 [PATCH v4 0/3] riscv: interrupt-controller: Add T-HEAD C900 ACLINT SSWI Inochi Amaoto
2024-10-22  4:02 ` [PATCH v4 1/3] dt-bindings: interrupt-controller: Add Sophgo SG2044 " Inochi Amaoto
2024-10-22  4:02 ` [PATCH v4 2/3] irqchip: add T-HEAD C900 ACLINT SSWI driver Inochi Amaoto
2024-10-29  7:45   ` Thomas Gleixner
2024-10-31  5:07     ` Anup Patel
2024-10-31  5:45       ` Inochi Amaoto
2024-10-22  4:02 ` [PATCH v4 3/3] riscv: defconfig: Enable T-HEAD C900 ACLINT SSWI drivers Inochi Amaoto

This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).