[PATCH v2 0/2] nvmem: qfprom: add Qualcomm SAR2130P support

[PATCH v2 0/2] nvmem: qfprom: add Qualcomm SAR2130P support

[Dmitry Baryshkov]

Pick up a fix from msm-5.x kernels and add compatible for the Qualcomm
SAR2130P platform.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
Changes in v2:
- Picked up required patch from QCLinux.
- Link to v1: https://lore.kernel.org/r/20241017-sar2130p-nvmem-v1-1-6cc32789afc6@linaro.org

---
Dmitry Baryshkov (1):
      dt-bindings: nvmem: qcom,qfprom: Add SAR2130P compatible

Naman Jain (1):
      nvmem: qfprom: Ensure access to qfprom is word aligned

 .../devicetree/bindings/nvmem/qcom,qfprom.yaml        |  1 +
 drivers/nvmem/qfprom.c                                | 19 ++++++++++++++++---
 2 files changed, 17 insertions(+), 3 deletions(-)
---
base-commit: a39230ecf6b3057f5897bc4744a790070cfbe7a8
change-id: 20241017-sar2130p-nvmem-5f856d99bbb7

Best regards,
-- 
Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

[PATCH v2 1/2] nvmem: qfprom: Ensure access to qfprom is word aligned

[Dmitry Baryshkov]

From: Naman Jain <quic_namajain@quicinc.com>

Add logic for alignment of address for reading in qfprom driver to avoid
NOC error issues due to unaligned access. The problem manifests on the
SAR2130P platform, but in msm-5.x kernels the fix is applied
uncoditionally. Follow this approach and uncoditionally perform aligned
reads.

Fixes: 4ab11996b489 ("nvmem: qfprom: Add Qualcomm QFPROM support.")
Signed-off-by: Naman Jain <quic_namajain@quicinc.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 drivers/nvmem/qfprom.c | 19 ++++++++++++++++---
 1 file changed, 16 insertions(+), 3 deletions(-)

diff --git a/drivers/nvmem/qfprom.c b/drivers/nvmem/qfprom.c
index 116a39e804c70b4a0374f8ea3ac6ba1dd612109d..cad319e7bfcf34c9b9ab15eb331efda822699cce 100644
--- a/drivers/nvmem/qfprom.c
+++ b/drivers/nvmem/qfprom.c
@@ -322,15 +322,28 @@ static int qfprom_reg_read(void *context,
 {
 	struct qfprom_priv *priv = context;
 	u8 *val = _val;
-	int i = 0, words = bytes;
+	int buf_start, buf_end, index, i = 0;
 	void __iomem *base = priv->qfpcorrected;
+	char *buffer = NULL;
+	u32 read_val;
 
 	if (read_raw_data && priv->qfpraw)
 		base = priv->qfpraw;
+	buf_start = ALIGN_DOWN(reg, 4);
+	buf_end = ALIGN(reg + bytes, 4);
+	buffer = kzalloc(buf_end - buf_start, GFP_KERNEL);
+	if (!buffer) {
+		pr_err("memory allocation failed in %s\n", __func__);
+		return -ENOMEM;
+	}
 
-	while (words--)
-		*val++ = readb(base + reg + i++);
+	for (index = buf_start; index < buf_end; index += 4, i += 4) {
+		read_val = readl_relaxed(base + index);
+		memcpy(buffer + i, &read_val, 4);
+	}
 
+	memcpy(val, buffer + reg % 4, bytes);
+	kfree(buffer);
 	return 0;
 }
 

-- 
2.39.5

[PATCH v2 2/2] dt-bindings: nvmem: qcom,qfprom: Add SAR2130P compatible

[Dmitry Baryshkov]

Document compatible for the QFPROM on SAR2130P platform.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml b/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml
index 80845c722ae46611c722effeaaf014a0caf76e4a..9755b31946bf9d4c1055a993145d06c274b61a37 100644
--- a/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml
+++ b/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml
@@ -32,6 +32,7 @@ properties:
           - qcom,msm8998-qfprom
           - qcom,qcm2290-qfprom
           - qcom,qcs404-qfprom
+          - qcom,sar2130p-qfprom
           - qcom,sc7180-qfprom
           - qcom,sc7280-qfprom
           - qcom,sc8280xp-qfprom

-- 
2.39.5

Re: [PATCH v2 2/2] dt-bindings: nvmem: qcom,qfprom: Add SAR2130P compatible

[Krzysztof Kozlowski]

On Sun, Oct 27, 2024 at 01:42:34AM +0300, Dmitry Baryshkov wrote:
> Document compatible for the QFPROM on SAR2130P platform.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof

Re: [PATCH v2 0/2] nvmem: qfprom: add Qualcomm SAR2130P support

[Dmitry Baryshkov]

On Sun, Oct 27, 2024 at 01:42:32AM +0300, Dmitry Baryshkov wrote:
> Pick up a fix from msm-5.x kernels and add compatible for the Qualcomm
> SAR2130P platform.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> Changes in v2:
> - Picked up required patch from QCLinux.
> - Link to v1: https://lore.kernel.org/r/20241017-sar2130p-nvmem-v1-1-6cc32789afc6@linaro.org

These two patches have been sent two weeks ago, but got no response from
the maintainers. Is there any reason for that? Srinivas, is the
subsystem being maintained or should we change it to 'S: Odd Fixes'?

-- 
With best wishes
Dmitry

Re: [PATCH v2 0/2] nvmem: qfprom: add Qualcomm SAR2130P support

[Dmitry Baryshkov]

On Fri, Nov 15, 2024 at 09:59:58AM +0200, Dmitry Baryshkov wrote:
> On Sun, Oct 27, 2024 at 01:42:32AM +0300, Dmitry Baryshkov wrote:
> > Pick up a fix from msm-5.x kernels and add compatible for the Qualcomm
> > SAR2130P platform.
> > 
> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> > ---
> > Changes in v2:
> > - Picked up required patch from QCLinux.
> > - Link to v1: https://lore.kernel.org/r/20241017-sar2130p-nvmem-v1-1-6cc32789afc6@linaro.org
> 
> These two patches have been sent two weeks ago, but got no response from
> the maintainers. Is there any reason for that? Srinivas, is the
> subsystem being maintained or should we change it to 'S: Odd Fixes'?

Another two weeks and still no response. Yes, we are in the merge
window, so I don't expect the patches to be applied. However it would
have been nice to get a feedback from the maintainer.

-- 
With best wishes
Dmitry

Re: [PATCH v2 1/2] nvmem: qfprom: Ensure access to qfprom is word aligned

[Srinivas Kandagatla]

On 26/10/2024 23:42, Dmitry Baryshkov wrote:
> From: Naman Jain <quic_namajain@quicinc.com>
> 
> Add logic for alignment of address for reading in qfprom driver to avoid
> NOC error issues due to unaligned access. The problem manifests on the
> SAR2130P platform, but in msm-5.x kernels the fix is applied

Is this only issue with SAR2130P?

> uncoditionally. Follow this approach and uncoditionally perform aligned
> reads.

If there is a need of having proper register alignment this should go as 
part of the nvmem_config->stride and word_size configuration and not in 
reg_read callbacks.


--srini

> 
> Fixes: 4ab11996b489 ("nvmem: qfprom: Add Qualcomm QFPROM support.")
> Signed-off-by: Naman Jain <quic_namajain@quicinc.com>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
>   drivers/nvmem/qfprom.c | 19 ++++++++++++++++---
>   1 file changed, 16 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/nvmem/qfprom.c b/drivers/nvmem/qfprom.c
> index 116a39e804c70b4a0374f8ea3ac6ba1dd612109d..cad319e7bfcf34c9b9ab15eb331efda822699cce 100644
> --- a/drivers/nvmem/qfprom.c
> +++ b/drivers/nvmem/qfprom.c
> @@ -322,15 +322,28 @@ static int qfprom_reg_read(void *context,
>   {
>   	struct qfprom_priv *priv = context;
>   	u8 *val = _val;
> -	int i = 0, words = bytes;
> +	int buf_start, buf_end, index, i = 0;
>   	void __iomem *base = priv->qfpcorrected;
> +	char *buffer = NULL;
> +	u32 read_val;
>   
>   	if (read_raw_data && priv->qfpraw)
>   		base = priv->qfpraw;
> +	buf_start = ALIGN_DOWN(reg, 4);
> +	buf_end = ALIGN(reg + bytes, 4);
> +	buffer = kzalloc(buf_end - buf_start, GFP_KERNEL);
> +	if (!buffer) {
> +		pr_err("memory allocation failed in %s\n", __func__);
> +		return -ENOMEM;
> +	}
>   
> -	while (words--)
> -		*val++ = readb(base + reg + i++);
> +	for (index = buf_start; index < buf_end; index += 4, i += 4) {
> +		read_val = readl_relaxed(base + index);
> +		memcpy(buffer + i, &read_val, 4);
> +	}
>   
> +	memcpy(val, buffer + reg % 4, bytes);
> +	kfree(buffer);
>   	return 0;
>   }
>   
> 

Re: [PATCH v2 1/2] nvmem: qfprom: Ensure access to qfprom is word aligned

[Dmitry Baryshkov]

On Mon, Dec 09, 2024 at 09:55:14AM +0000, Srinivas Kandagatla wrote:
> 
> 
> On 26/10/2024 23:42, Dmitry Baryshkov wrote:
> > From: Naman Jain <quic_namajain@quicinc.com>
> > 
> > Add logic for alignment of address for reading in qfprom driver to avoid
> > NOC error issues due to unaligned access. The problem manifests on the
> > SAR2130P platform, but in msm-5.x kernels the fix is applied
> 
> Is this only issue with SAR2130P?

I don't know. I know that it manifests on SAR2130P, but in the vendor
kernels the fix is applied to all the platforms.

> 
> > uncoditionally. Follow this approach and uncoditionally perform aligned
> > reads.
> 
> If there is a need of having proper register alignment this should go as
> part of the nvmem_config->stride and word_size configuration and not in
> reg_read callbacks.

Thanks, I'll explore that option. Indeed, it might be easier to handle.

-- 
With best wishes
Dmitry

Re: [PATCH v2 1/2] nvmem: qfprom: Ensure access to qfprom is word aligned

[Akhil P Oommen]

On 12/9/2024 4:23 PM, Dmitry Baryshkov wrote:
> On Mon, Dec 09, 2024 at 09:55:14AM +0000, Srinivas Kandagatla wrote:
>>
>>
>> On 26/10/2024 23:42, Dmitry Baryshkov wrote:
>>> From: Naman Jain <quic_namajain@quicinc.com>
>>>
>>> Add logic for alignment of address for reading in qfprom driver to avoid
>>> NOC error issues due to unaligned access. The problem manifests on the
>>> SAR2130P platform, but in msm-5.x kernels the fix is applied
>>
>> Is this only issue with SAR2130P?

This is applicable to all chipsets with sys arch newer than Snapdragon 8
Gen 1.

> 
> I don't know. I know that it manifests on SAR2130P, but in the vendor
> kernels the fix is applied to all the platforms.
> 
>>
>>> uncoditionally. Follow this approach and uncoditionally perform aligned
>>> reads.
>>
>> If there is a need of having proper register alignment this should go as
>> part of the nvmem_config->stride and word_size configuration and not in
>> reg_read callbacks.
> 
> Thanks, I'll explore that option. Indeed, it might be easier to handle.

Dmitry, any update here? I need similar change for X1E GPU speedbin support.

-Akhil

> 

Re: [PATCH v2 1/2] nvmem: qfprom: Ensure access to qfprom is word aligned

[Dmitry Baryshkov]

On Mon, Dec 30, 2024 at 01:13:08PM +0530, Akhil P Oommen wrote:
> On 12/9/2024 4:23 PM, Dmitry Baryshkov wrote:
> > On Mon, Dec 09, 2024 at 09:55:14AM +0000, Srinivas Kandagatla wrote:
> >>
> >>
> >> On 26/10/2024 23:42, Dmitry Baryshkov wrote:
> >>> From: Naman Jain <quic_namajain@quicinc.com>
> >>>
> >>> Add logic for alignment of address for reading in qfprom driver to avoid
> >>> NOC error issues due to unaligned access. The problem manifests on the
> >>> SAR2130P platform, but in msm-5.x kernels the fix is applied
> >>
> >> Is this only issue with SAR2130P?
> 
> This is applicable to all chipsets with sys arch newer than Snapdragon 8
> Gen 1.
> 
> > 
> > I don't know. I know that it manifests on SAR2130P, but in the vendor
> > kernels the fix is applied to all the platforms.
> > 
> >>
> >>> uncoditionally. Follow this approach and uncoditionally perform aligned
> >>> reads.
> >>
> >> If there is a need of having proper register alignment this should go as
> >> part of the nvmem_config->stride and word_size configuration and not in
> >> reg_read callbacks.
> > 
> > Thanks, I'll explore that option. Indeed, it might be easier to handle.
> 
> Dmitry, any update here? I need similar change for X1E GPU speedbin support.

Excuse me for the delay, I've sent v3, reworking the series as
requested:

https://lore.kernel.org/linux-arm-msm/20250104-sar2130p-nvmem-v3-0-a94e0b7de2fa@linaro.org/

-- 
With best wishes
Dmitry

Re: [PATCH v2 1/2] nvmem: qfprom: Ensure access to qfprom is word aligned

[Akhil P Oommen]

On 1/4/2025 1:10 PM, Dmitry Baryshkov wrote:
> On Mon, Dec 30, 2024 at 01:13:08PM +0530, Akhil P Oommen wrote:
>> On 12/9/2024 4:23 PM, Dmitry Baryshkov wrote:
>>> On Mon, Dec 09, 2024 at 09:55:14AM +0000, Srinivas Kandagatla wrote:
>>>>
>>>>
>>>> On 26/10/2024 23:42, Dmitry Baryshkov wrote:
>>>>> From: Naman Jain <quic_namajain@quicinc.com>
>>>>>
>>>>> Add logic for alignment of address for reading in qfprom driver to avoid
>>>>> NOC error issues due to unaligned access. The problem manifests on the
>>>>> SAR2130P platform, but in msm-5.x kernels the fix is applied
>>>>
>>>> Is this only issue with SAR2130P?
>>
>> This is applicable to all chipsets with sys arch newer than Snapdragon 8
>> Gen 1.
>>
>>>
>>> I don't know. I know that it manifests on SAR2130P, but in the vendor
>>> kernels the fix is applied to all the platforms.
>>>
>>>>
>>>>> uncoditionally. Follow this approach and uncoditionally perform aligned
>>>>> reads.
>>>>
>>>> If there is a need of having proper register alignment this should go as
>>>> part of the nvmem_config->stride and word_size configuration and not in
>>>> reg_read callbacks.
>>>
>>> Thanks, I'll explore that option. Indeed, it might be easier to handle.
>>
>> Dmitry, any update here? I need similar change for X1E GPU speedbin support.
> 
> Excuse me for the delay, I've sent v3, reworking the series as
> requested:
> 
> https://lore.kernel.org/linux-arm-msm/20250104-sar2130p-nvmem-v3-0-a94e0b7de2fa@linaro.org/
> 

No issues. Thanks a lot for getting this done.

-Akhil.