From: Frank Li <Frank.Li@nxp.com>
To: "Rob Herring" <robh@kernel.org>,
"Saravana Kannan" <saravanak@google.com>,
"Jingoo Han" <jingoohan1@gmail.com>,
"Manivannan Sadhasivam" <manivannan.sadhasivam@linaro.org>,
"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
"Krzysztof Wilczyński" <kw@linux.com>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Richard Zhu" <hongxing.zhu@nxp.com>,
"Lucas Stach" <l.stach@pengutronix.de>,
"Shawn Guo" <shawnguo@kernel.org>,
"Sascha Hauer" <s.hauer@pengutronix.de>,
"Pengutronix Kernel Team" <kernel@pengutronix.de>,
"Fabio Estevam" <festevam@gmail.com>
Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
imx@lists.linux.dev, Frank Li <Frank.Li@nxp.com>
Subject: [PATCH v6 6/7] PCI: imx6: Pass correct sub mode when calling phy_set_mode_ext()
Date: Mon, 28 Oct 2024 15:06:00 -0400 [thread overview]
Message-ID: <20241028-pci_fixup_addr-v6-6-ebebcd8fd4ff@nxp.com> (raw)
In-Reply-To: <20241028-pci_fixup_addr-v6-0-ebebcd8fd4ff@nxp.com>
Fix hardcoding to Root Complex (RC) mode by adding a drvdata mode check.
Pass PHY_MODE_PCIE_EP if the PCI controller operates in Endpoint (EP) mode.
Fixes: 8026f2d8e8a9 ("PCI: imx6: Call common PHY API to set mode, speed, and submode")
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Richard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
Change from v3->v6
- none
Change from v2->v3
- Add mani's review tag
---
drivers/pci/controller/dwc/pci-imx6.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
index 533905b3942a1..8102a02a00b38 100644
--- a/drivers/pci/controller/dwc/pci-imx6.c
+++ b/drivers/pci/controller/dwc/pci-imx6.c
@@ -960,7 +960,9 @@ static int imx_pcie_host_init(struct dw_pcie_rp *pp)
goto err_clk_disable;
}
- ret = phy_set_mode_ext(imx_pcie->phy, PHY_MODE_PCIE, PHY_MODE_PCIE_RC);
+ ret = phy_set_mode_ext(imx_pcie->phy, PHY_MODE_PCIE,
+ imx_pcie->drvdata->mode == DW_PCIE_EP_TYPE ?
+ PHY_MODE_PCIE_EP : PHY_MODE_PCIE_RC);
if (ret) {
dev_err(dev, "unable to set PCIe PHY mode\n");
goto err_phy_exit;
--
2.34.1
next prev parent reply other threads:[~2024-10-28 19:06 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-10-28 19:05 [PATCH v6 0/7] PCI: dwc: opitimaze RC Host/EP pci_fixup_addr() Frank Li
2024-10-28 19:05 ` [PATCH v6 1/7] of: address: Add parent_bus_addr to struct of_pci_range Frank Li
2024-10-28 19:05 ` [PATCH v6 2/7] PCI: dwc: Using parent_bus_addr in of_range to eliminate cpu_addr_fixup() Frank Li
2024-10-29 5:03 ` kernel test robot
2024-10-29 7:18 ` kernel test robot
2024-10-28 19:05 ` [PATCH v6 3/7] PCI: dwc: ep: Add bus_addr_base for outbound window Frank Li
2024-10-28 19:05 ` [PATCH v6 4/7] PCI: imx6: Remove cpu_addr_fixup() Frank Li
2024-10-28 19:05 ` [PATCH v6 5/7] dt-bindings: PCI: fsl,imx6q-pcie-ep: Add compatible string fsl,imx8q-pcie-ep Frank Li
2024-10-28 19:06 ` Frank Li [this message]
2024-10-28 19:06 ` [PATCH v6 7/7] PCI: imx6: Add i.MX8Q PCIe Endpoint (EP) support Frank Li
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