Re: [PATCH v6 2/7] PCI: dwc: Using parent_bus_addr in of_range to eliminate cpu_addr_fixup()

[kernel test robot <lkp@intel.com>]

Hi Frank,

kernel test robot noticed the following build errors:

[auto build test ERROR on 9852d85ec9d492ebef56dc5f229416c925758edc]

url:    https://github.com/intel-lab-lkp/linux/commits/Frank-Li/of-address-Add-parent_bus_addr-to-struct-of_pci_range/20241029-030935
base:   9852d85ec9d492ebef56dc5f229416c925758edc
patch link:    https://lore.kernel.org/r/20241028-pci_fixup_addr-v6-2-ebebcd8fd4ff%40nxp.com
patch subject: [PATCH v6 2/7] PCI: dwc: Using parent_bus_addr in of_range to eliminate cpu_addr_fixup()
config: arm-defconfig (https://download.01.org/0day-ci/archive/20241029/202410291546.kvgEWJv7-lkp@intel.com/config)
compiler: clang version 14.0.6 (https://github.com/llvm/llvm-project f28c006a5895fc0e329fe15fead81e37457cb1d1)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20241029/202410291546.kvgEWJv7-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202410291546.kvgEWJv7-lkp@intel.com/

All errors (new ones prefixed by >>):

>> drivers/pci/controller/dwc/pcie-designware-host.c:782:55: error: incompatible pointer types passing 'u64 *' (aka 'unsigned long long *') to parameter of type 'resource_size_t *' (aka 'unsigned int *') [-Werror,-Wincompatible-pointer-types]
                   if (dw_pcie_get_untranslate_addr(pci, atu.pci_addr, &atu.cpu_addr))
                                                                       ^~~~~~~~~~~~~
   drivers/pci/controller/dwc/pcie-designware-host.c:422:23: note: passing argument to parameter 'i_addr' here
                                           resource_size_t *i_addr)
                                                            ^
   1 error generated.


vim +782 drivers/pci/controller/dwc/pcie-designware-host.c

   745	
   746	static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp)
   747	{
   748		struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
   749		struct dw_pcie_ob_atu_cfg atu = { 0 };
   750		struct resource_entry *entry;
   751		int i, ret;
   752	
   753		/* Note the very first outbound ATU is used for CFG IOs */
   754		if (!pci->num_ob_windows) {
   755			dev_err(pci->dev, "No outbound iATU found\n");
   756			return -EINVAL;
   757		}
   758	
   759		/*
   760		 * Ensure all out/inbound windows are disabled before proceeding with
   761		 * the MEM/IO (dma-)ranges setups.
   762		 */
   763		for (i = 0; i < pci->num_ob_windows; i++)
   764			dw_pcie_disable_atu(pci, PCIE_ATU_REGION_DIR_OB, i);
   765	
   766		for (i = 0; i < pci->num_ib_windows; i++)
   767			dw_pcie_disable_atu(pci, PCIE_ATU_REGION_DIR_IB, i);
   768	
   769		i = 0;
   770		resource_list_for_each_entry(entry, &pp->bridge->windows) {
   771			if (resource_type(entry->res) != IORESOURCE_MEM)
   772				continue;
   773	
   774			if (pci->num_ob_windows <= ++i)
   775				break;
   776	
   777			atu.index = i;
   778			atu.type = PCIE_ATU_TYPE_MEM;
   779			atu.cpu_addr = entry->res->start;
   780			atu.pci_addr = entry->res->start - entry->offset;
   781	
 > 782			if (dw_pcie_get_untranslate_addr(pci, atu.pci_addr, &atu.cpu_addr))
   783				return -EINVAL;
   784	
   785			/* Adjust iATU size if MSG TLP region was allocated before */
   786			if (pp->msg_res && pp->msg_res->parent == entry->res)
   787				atu.size = resource_size(entry->res) -
   788						resource_size(pp->msg_res);
   789			else
   790				atu.size = resource_size(entry->res);
   791	
   792			ret = dw_pcie_prog_outbound_atu(pci, &atu);
   793			if (ret) {
   794				dev_err(pci->dev, "Failed to set MEM range %pr\n",
   795					entry->res);
   796				return ret;
   797			}
   798		}
   799	
   800		if (pp->io_size) {
   801			if (pci->num_ob_windows > ++i) {
   802				atu.index = i;
   803				atu.type = PCIE_ATU_TYPE_IO;
   804				atu.cpu_addr = pp->io_base;
   805				atu.pci_addr = pp->io_bus_addr;
   806				atu.size = pp->io_size;
   807	
   808				ret = dw_pcie_prog_outbound_atu(pci, &atu);
   809				if (ret) {
   810					dev_err(pci->dev, "Failed to set IO range %pr\n",
   811						entry->res);
   812					return ret;
   813				}
   814			} else {
   815				pp->cfg0_io_shared = true;
   816			}
   817		}
   818	
   819		if (pci->num_ob_windows <= i)
   820			dev_warn(pci->dev, "Ranges exceed outbound iATU size (%d)\n",
   821				 pci->num_ob_windows);
   822	
   823		pp->msg_atu_index = i;
   824	
   825		i = 0;
   826		resource_list_for_each_entry(entry, &pp->bridge->dma_ranges) {
   827			if (resource_type(entry->res) != IORESOURCE_MEM)
   828				continue;
   829	
   830			if (pci->num_ib_windows <= i)
   831				break;
   832	
   833			ret = dw_pcie_prog_inbound_atu(pci, i++, PCIE_ATU_TYPE_MEM,
   834						       entry->res->start,
   835						       entry->res->start - entry->offset,
   836						       resource_size(entry->res));
   837			if (ret) {
   838				dev_err(pci->dev, "Failed to set DMA range %pr\n",
   839					entry->res);
   840				return ret;
   841			}
   842		}
   843	
   844		if (pci->num_ib_windows <= i)
   845			dev_warn(pci->dev, "Dma-ranges exceed inbound iATU size (%u)\n",
   846				 pci->num_ib_windows);
   847	
   848		return 0;
   849	}
   850	

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