From: Lothar Rubusch <l.rubusch@gmail.com>
To: robh@kernel.org, krzk+dt@kernel.org, a.fatoum@pengutronix.de
Cc: conor+dt@kernel.org, dinguyen@kernel.org, marex@denx.de,
s.trumtrar@pengutronix.de, alexandre.torgue@foss.st.com,
joabreu@synopsys.com, davem@davemloft.net, edumazet@google.com,
kuba@kernel.org, pabeni@redhat.com, mcoquelin.stm32@gmail.com,
netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com,
linux-arm-kernel@lists.infradead.org, l.rubusch@gmail.com,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: [PATCH v4 14/23] ARM: dts: socfpga: add Enclustra base-board dtsi
Date: Tue, 29 Oct 2024 20:23:40 +0000 [thread overview]
Message-ID: <20241029202349.69442-15-l.rubusch@gmail.com> (raw)
In-Reply-To: <20241029202349.69442-1-l.rubusch@gmail.com>
Add generic Enclustra base-board support for the Mercury+ PE1, the
Mercury+ PE3 and the Mercury+ ST1 board. The carrier boards can be
freely combined with the SoMs Mercury+ AA1, Mercury SA1 and
Mercury+ SA2.
Signed-off-by: Andreas Buerkler <andreas.buerkler@enclustra.com>
Signed-off-by: Lothar Rubusch <l.rubusch@gmail.com>
---
.../socfpga_enclustra_mercury_pe1.dtsi | 33 +++++++++++
.../socfpga_enclustra_mercury_pe3.dtsi | 55 +++++++++++++++++++
.../socfpga_enclustra_mercury_st1.dtsi | 15 +++++
3 files changed, 103 insertions(+)
create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_pe1.dtsi
create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_pe3.dtsi
create mode 100644 arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_st1.dtsi
diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_pe1.dtsi b/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_pe1.dtsi
new file mode 100644
index 000000000..abc4bfb7f
--- /dev/null
+++ b/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_pe1.dtsi
@@ -0,0 +1,33 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com
+ */
+
+&i2c_encl {
+ status = "okay";
+
+ eeprom@57 {
+ status = "okay";
+ compatible = "microchip,24c128";
+ reg = <0x57>;
+ pagesize = <64>;
+ label = "user eeprom";
+ address-width = <16>;
+ };
+
+ lm96080: temperature-sensor@2f {
+ status = "okay";
+ compatible = "national,lm80";
+ reg = <0x2f>;
+ };
+
+ si5338: clock-controller@70 {
+ compatible = "silabs,si5338";
+ reg = <0x70>;
+ };
+
+};
+
+&i2c_encl_fpga {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_pe3.dtsi b/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_pe3.dtsi
new file mode 100644
index 000000000..bc57b0680
--- /dev/null
+++ b/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_pe3.dtsi
@@ -0,0 +1,55 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com
+ */
+
+&i2c_encl {
+ i2c-mux@74 {
+ status = "okay";
+ compatible = "nxp,pca9547";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x74>;
+
+ i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ eeprom@56 {
+ status = "okay";
+ compatible = "microchip,24c128";
+ reg = <0x56>;
+ pagesize = <64>;
+ label = "user eeprom";
+ address-width = <16>;
+ };
+
+ lm96080: temperature-sensor@2f {
+ status = "okay";
+ compatible = "national,lm80";
+ reg = <0x2f>;
+ };
+
+ pcal6416: gpio@20 {
+ status = "okay";
+ compatible = "nxp,pcal6416";
+ reg = <0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+ };
+ };
+};
+
+&i2c_encl_fpga {
+ status = "okay";
+
+ i2c-mux@75 {
+ status = "okay";
+ compatible = "nxp,pca9547";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x75>;
+ };
+};
diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_st1.dtsi b/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_st1.dtsi
new file mode 100644
index 000000000..4c00475f4
--- /dev/null
+++ b/arch/arm/boot/dts/intel/socfpga/socfpga_enclustra_mercury_st1.dtsi
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * Copyright (C) 2024 Enclustra GmbH - https://www.enclustra.com
+ */
+
+&i2c_encl {
+ si5338: clock-controller@70 {
+ compatible = "silabs,si5338";
+ reg = <0x70>;
+ };
+};
+
+&i2c_encl_fpga {
+ status = "okay";
+};
--
2.25.1
next prev parent reply other threads:[~2024-10-29 20:24 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-10-29 20:23 [PATCH v4 00/23] Add Enclustra Arria10 and Cyclone5 SoMs Lothar Rubusch
2024-10-29 20:23 ` [PATCH v4 01/23] ARM: dts: socfpga: fix typo Lothar Rubusch
2024-10-29 20:23 ` [PATCH v4 02/23] ARM: dts: socfpga: align bus name with bindings Lothar Rubusch
2024-10-29 20:23 ` [PATCH v4 03/23] ARM: dts: socfpga: align dma name with binding Lothar Rubusch
2024-10-29 20:23 ` [PATCH v4 04/23] ARM: dts: socfpga: align fpga-region name Lothar Rubusch
2024-10-29 20:23 ` [PATCH v4 05/23] ARM: dts: socfpga: add label to clock manager Lothar Rubusch
2024-10-29 20:23 ` [PATCH v4 06/23] ARM: dts: socfpga: add missing cells properties Lothar Rubusch
2024-10-29 20:23 ` [PATCH v4 07/23] ARM: dts: socfpga: fix missing ranges Lothar Rubusch
2024-10-29 20:23 ` [PATCH v4 08/23] ARM: dts: socfpga: add clock-frequency property Lothar Rubusch
2024-10-29 20:23 ` [PATCH v4 09/23] ARM: dts: socfpga: add ranges property to sram Lothar Rubusch
2024-10-29 20:23 ` [PATCH v4 10/23] ARM: dts: socfpga: remove arria10 reset-names Lothar Rubusch
2024-10-29 20:23 ` [PATCH v4 11/23] net: stmmac: add support for dwmac 3.72a Lothar Rubusch
2024-11-01 19:35 ` Rob Herring
2024-11-02 11:58 ` Lothar Rubusch
2024-10-29 20:23 ` [PATCH v4 12/23] dt-bindings: net: snps,dwmac: add support for Arria10 Lothar Rubusch
2024-10-29 21:58 ` Jakub Kicinski
2024-11-01 19:39 ` Rob Herring (Arm)
2024-10-29 20:23 ` [PATCH v4 13/23] ARM: dts: socfpga: add Enclustra boot-mode dtsi Lothar Rubusch
2024-10-29 20:23 ` Lothar Rubusch [this message]
2024-10-29 20:23 ` [PATCH v4 15/23] ARM: dts: socfpga: add Enclustra Mercury SA1 Lothar Rubusch
2024-10-29 20:23 ` [PATCH v4 16/23] dt-bindings: altera: " Lothar Rubusch
2024-10-29 20:23 ` [PATCH v4 17/23] ARM: dts: socfpga: add Enclustra Mercury+ SA2 Lothar Rubusch
2024-10-29 20:23 ` [PATCH v4 18/23] dt-bindings: altera: add binding for " Lothar Rubusch
2024-10-29 20:23 ` [PATCH v4 19/23] ARM: dts: socfpga: add Mercury AA1 combinations Lothar Rubusch
2024-10-29 20:23 ` [PATCH v4 20/23] dt-bindings: altera: " Lothar Rubusch
2024-10-29 20:23 ` [PATCH v4 21/23] ARM: dts: socfpga: removal of generic PE1 dts Lothar Rubusch
2024-10-29 20:23 ` [PATCH v4 22/23] dt-bindings: altera: " Lothar Rubusch
2024-10-29 20:23 ` [PATCH v4 23/23] ARM: dts: socfpga: add Enclustra SoM dts files Lothar Rubusch
2024-10-30 17:04 ` [PATCH v4 00/23] Add Enclustra Arria10 and Cyclone5 SoMs Rob Herring (Arm)
2024-10-31 9:04 ` Lothar Rubusch
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