Re: [PATCH v9 4/8] iio: dac: adi-axi-dac: extend features

[Jonathan Cameron <jic23@kernel.org>]

On Tue, 29 Oct 2024 09:13:42 +0100
Nuno Sá <noname.nuno@gmail.com> wrote:

> On Mon, 2024-10-28 at 22:45 +0100, Angelo Dureghello wrote:
> > From: Angelo Dureghello <adureghello@baylibre.com>
> > 
> > Extend AXI-DAC backend with new features required to interface
> > to the ad3552r DAC. Mainly, a new compatible string is added to
> > support the ad3552r-axi DAC IP, very similar to the generic DAC
> > IP but with some customizations to work with the ad3552r.
> > 
> > Then, a series of generic functions has been added to match with
> > ad3552r needs. Function names has been kept generic as much as
> > possible, to allow re-utilization from other frontend drivers.
> > 
> > Signed-off-by: Angelo Dureghello <adureghello@baylibre.com>
> > ---  
> 
> Hi Angelo,
> 
> Small stuff that Jonathan might be able to change while applying... With that:
> 
> Reviewed-by: Nuno Sa <nuno.sa@analog.com>
> 
> >  drivers/iio/dac/adi-axi-dac.c | 256 +++++++++++++++++++++++++++++++++++++++--
> > -
> >  1 file changed, 242 insertions(+), 14 deletions(-)
> > 
> > diff --git a/drivers/iio/dac/adi-axi-dac.c b/drivers/iio/dac/adi-axi-dac.c
> > index 04193a98616e..155d04ca2315 100644
> > --- a/drivers/iio/dac/adi-axi-dac.c
> > +++ b/drivers/iio/dac/adi-axi-dac.c
> > @@ -46,9 +46,28 @@
> >  #define AXI_DAC_CNTRL_1_REG			0x0044
> >  #define   AXI_DAC_CNTRL_1_SYNC			BIT(0)
> >  #define AXI_DAC_CNTRL_2_REG			0x0048
> > +#define   AXI_DAC_CNTRL_2_SDR_DDR_N		BIT(16)
> > +#define   AXI_DAC_CNTRL_2_SYMB_8B		BIT(14)
> >  #define   ADI_DAC_CNTRL_2_R1_MODE		BIT(5)
> > +#define   AXI_DAC_CNTRL_2_UNSIGNED_DATA		BIT(4)
> > +#define AXI_DAC_STATUS_1_REG			0x0054
> > +#define AXI_DAC_STATUS_2_REG			0x0058
> >  #define AXI_DAC_DRP_STATUS_REG			0x0074
> >  #define   AXI_DAC_DRP_STATUS_DRP_LOCKED		BIT(17)
> > +#define AXI_DAC_CUSTOM_RD_REG			0x0080
> > +#define AXI_DAC_CUSTOM_WR_REG			0x0084
> > +#define   AXI_DAC_CUSTOM_WR_DATA_8		GENMASK(23, 16)
> > +#define   AXI_DAC_CUSTOM_WR_DATA_16		GENMASK(23, 8)
> > +#define AXI_DAC_UI_STATUS_REG			0x0088
> > +#define   AXI_DAC_UI_STATUS_IF_BUSY		BIT(4)
> > +#define AXI_DAC_CUSTOM_CTRL_REG			0x008C
> > +#define   AXI_DAC_CUSTOM_CTRL_ADDRESS		GENMASK(31, 24)
> > +#define   AXI_DAC_CUSTOM_CTRL_SYNCED_TRANSFER	BIT(2)
> > +#define   AXI_DAC_CUSTOM_CTRL_STREAM		BIT(1)
> > +#define   AXI_DAC_CUSTOM_CTRL_TRANSFER_DATA	BIT(0)
> > +
> > +#define
> > AXI_DAC_CUSTOM_CTRL_STREAM_ENABLE	(AXI_DAC_CUSTOM_CTRL_TRANSFER_DATA | \
> > +						 AXI_DAC_CUSTOM_CTRL_STREAM)
> >  
> >  /* DAC Channel controls */
> >  #define AXI_DAC_CHAN_CNTRL_1_REG(c)		(0x0400 + (c) * 0x40)
> > @@ -63,12 +82,21 @@
> >  #define AXI_DAC_CHAN_CNTRL_7_REG(c)		(0x0418 + (c) * 0x40)
> >  #define   AXI_DAC_CHAN_CNTRL_7_DATA_SEL		GENMASK(3, 0)
> >  
> > +#define AXI_DAC_RD_ADDR(x)			(BIT(7) | (x))
> > +
> >  /* 360 degrees in rad */
> >  #define AXI_DAC_2_PI_MEGA			6283190
> >  
> >  enum {
> >  	AXI_DAC_DATA_INTERNAL_TONE,
> >  	AXI_DAC_DATA_DMA = 2,
> > +	AXI_DAC_DATA_INTERNAL_RAMP_16BIT = 11,
> > +};
> > +
> > +struct axi_dac_info {
> > +	unsigned int version;
> > +	const struct iio_backend_info *backend_info;
> > +	bool has_dac_clk;
> >  };
> >  
> >  struct axi_dac_state {
> > @@ -79,9 +107,11 @@ struct axi_dac_state {
> >  	 * data/variables.
> >  	 */
> >  	struct mutex lock;
> > +	const struct axi_dac_info *info;
> >  	u64 dac_clk;
> >  	u32 reg_config;
> >  	bool int_tone;
> > +	int dac_clk_rate;
> >  };
> >  
> >  static int axi_dac_enable(struct iio_backend *back)
> > @@ -471,6 +501,11 @@ static int axi_dac_data_source_set(struct iio_backend
> > *back, unsigned int chan,
> >  					  AXI_DAC_CHAN_CNTRL_7_REG(chan),
> >  					  AXI_DAC_CHAN_CNTRL_7_DATA_SEL,
> >  					  AXI_DAC_DATA_DMA);
> > +	case IIO_BACKEND_INTERNAL_RAMP_16BIT:
> > +		return regmap_update_bits(st->regmap,
> > +					  AXI_DAC_CHAN_CNTRL_7_REG(chan),
> > +					  AXI_DAC_CHAN_CNTRL_7_DATA_SEL,
> > +					  AXI_DAC_DATA_INTERNAL_RAMP_16BIT);
> >  	default:
> >  		return -EINVAL;
> >  	}
> > @@ -528,6 +563,154 @@ static int axi_dac_reg_access(struct iio_backend *back,
> > unsigned int reg,
> >  	return regmap_write(st->regmap, reg, writeval);
> >  }
> >  
> > +static int axi_dac_ddr_enable(struct iio_backend *back)
> > +{
> > +	struct axi_dac_state *st = iio_backend_get_priv(back);
> > +
> > +	return regmap_clear_bits(st->regmap, AXI_DAC_CNTRL_2_REG,
> > +				 AXI_DAC_CNTRL_2_SDR_DDR_N);
> > +}
> > +
> > +static int axi_dac_ddr_disable(struct iio_backend *back)
> > +{
> > +	struct axi_dac_state *st = iio_backend_get_priv(back);
> > +
> > +	return regmap_set_bits(st->regmap, AXI_DAC_CNTRL_2_REG,
> > +			       AXI_DAC_CNTRL_2_SDR_DDR_N);
> > +}
> > +
> > +static int axi_dac_data_stream_enable(struct iio_backend *back)
> > +{
> > +	struct axi_dac_state *st = iio_backend_get_priv(back);
> > +
> > +	return regmap_set_bits(st->regmap, AXI_DAC_CUSTOM_CTRL_REG,
> > +			       AXI_DAC_CUSTOM_CTRL_STREAM_ENABLE);
> > +}
> > +
> > +static int axi_dac_data_stream_disable(struct iio_backend *back)
> > +{
> > +	struct axi_dac_state *st = iio_backend_get_priv(back);
> > +
> > +	return regmap_clear_bits(st->regmap, AXI_DAC_CUSTOM_CTRL_REG,
> > +				 AXI_DAC_CUSTOM_CTRL_STREAM_ENABLE);
> > +}
> > +
> > +static int axi_dac_data_transfer_addr(struct iio_backend *back, u32 address)
> > +{
> > +	struct axi_dac_state *st = iio_backend_get_priv(back);
> > +
> > +	if (address > FIELD_MAX(AXI_DAC_CUSTOM_CTRL_ADDRESS))
> > +		return -EINVAL;
> > +
> > +	/*
> > +	 * Sample register address, when the DAC is configured, or stream
> > +	 * start address when the FSM is in stream state.
> > +	 */
> > +	return regmap_update_bits(st->regmap, AXI_DAC_CUSTOM_CTRL_REG,
> > +				  AXI_DAC_CUSTOM_CTRL_ADDRESS,
> > +				  FIELD_PREP(AXI_DAC_CUSTOM_CTRL_ADDRESS,
> > +				  address));
> > +}
> > +
> > +static int axi_dac_data_format_set(struct iio_backend *back, unsigned int ch,
> > +				   const struct iio_backend_data_fmt *data)
> > +{
> > +	struct axi_dac_state *st = iio_backend_get_priv(back);
> > +
> > +	switch (data->type) {
> > +	case IIO_BACKEND_DATA_UNSIGNED:
> > +		return regmap_clear_bits(st->regmap, AXI_DAC_CNTRL_2_REG,
> > +					 AXI_DAC_CNTRL_2_UNSIGNED_DATA);
> > +	default:
> > +		return -EINVAL;
> > +	}
> > +}
> > +
> > +static int axi_dac_bus_reg_write_locked(struct iio_backend *back, u32 reg,
> > +					u32 val, size_t data_size)  
> 
> nit: this is actually unlocked and needs to be locked from the outside. So,
> unlocked could be a better suffix. But more importantly is the extra call to
> iio_backend_get_priv(). We can just pass *st directly from the outer function.

This naming always gets confusing. Are we naming the state, or what happens?

A lockdep marking just inside the function can be used to make it obvious
or the old __ prefix to say 'special, check the rules'.

Anyhow, I can tweak both issues, but will take another look at the
whole set sometime in next few days.
To sleepy to review now!

Jonathan


> 
> > +{
> > +	struct axi_dac_state *st = iio_backend_get_priv(back);
> > +	int ret;
> > +	u32 ival;
> > +
> > +	/*
> > +	 * Both AXI_DAC_CNTRL_2_REG and AXI_DAC_CUSTOM_WR_REG need to know
> > +	 * the data size. So keeping data size control here only,
> > +	 * since data size is mandatory for the current transfer.
> > +	 * DDR state handled separately by specific backend calls,
> > +	 * generally all raw register writes are SDR.
> > +	 */
> > +	if (data_size == sizeof(u16))
> > +		ival = FIELD_PREP(AXI_DAC_CUSTOM_WR_DATA_16, val);
> > +	else
> > +		ival = FIELD_PREP(AXI_DAC_CUSTOM_WR_DATA_8, val);
> > +
> > +	ret = regmap_write(st->regmap, AXI_DAC_CUSTOM_WR_REG, ival);
> > +	if (ret)
> > +		return ret;
> > +
> > +	if (data_size == sizeof(u8))
> > +		ret = regmap_set_bits(st->regmap, AXI_DAC_CNTRL_2_REG,
> > +				      AXI_DAC_CNTRL_2_SYMB_8B);
> > +	else
> > +		ret = regmap_clear_bits(st->regmap, AXI_DAC_CNTRL_2_REG,
> > +					AXI_DAC_CNTRL_2_SYMB_8B);
> > +	if (ret)
> > +		return ret;
> > +
> > +	ret = regmap_update_bits(st->regmap, AXI_DAC_CUSTOM_CTRL_REG,
> > +				 AXI_DAC_CUSTOM_CTRL_ADDRESS,
> > +				 FIELD_PREP(AXI_DAC_CUSTOM_CTRL_ADDRESS,
> > reg));
> > +	if (ret)
> > +		return ret;
> > +
> > +	ret = regmap_update_bits(st->regmap, AXI_DAC_CUSTOM_CTRL_REG,
> > +				 AXI_DAC_CUSTOM_CTRL_TRANSFER_DATA,
> > +				 AXI_DAC_CUSTOM_CTRL_TRANSFER_DATA);
> > +	if (ret)
> > +		return ret;
> > +
> > +	ret = regmap_read_poll_timeout(st->regmap,
> > +				AXI_DAC_UI_STATUS_REG, ival,
> > +				FIELD_GET(AXI_DAC_UI_STATUS_IF_BUSY, ival) ==
> > 0,
> > +				10, 100 * KILO);
> > +	if (ret == -ETIMEDOUT)
> > +		dev_err(st->dev, "AXI read timeout\n");
> > +
> > +	/* Cleaning always AXI_DAC_CUSTOM_CTRL_TRANSFER_DATA */
> > +	return regmap_clear_bits(st->regmap, AXI_DAC_CUSTOM_CTRL_REG,
> > +				 AXI_DAC_CUSTOM_CTRL_TRANSFER_DATA);
> > +}
> > +
> > +static int axi_dac_bus_reg_write(struct iio_backend *back, u32 reg,
> > +					u32 val, size_t data_size)
> > +{
> > +	struct axi_dac_state *st = iio_backend_get_priv(back);
> > +
> > +	guard(mutex)(&st->lock);
> > +	return axi_dac_bus_reg_write_locked(back, reg, val, data_size);
> > +}
> > +  
> 
> Also just realized that the above read()/write() functions could make more sense
> in the patch making the device a "bus controller". But well, not that important
> I guess.
> 
> - Nuno Sá
> 
>