From: Conor Dooley <conor@kernel.org>
To: "Clément Léger" <cleger@rivosinc.com>
Cc: Inochi Amaoto <inochiama@gmail.com>,
Jonathan Corbet <corbet@lwn.net>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Evan Green <evan@rivosinc.com>,
Charlie Jenkins <charlie@rivosinc.com>,
Andrew Jones <ajones@ventanamicro.com>,
Andy Chiu <andybnac@gmail.com>, Xiao Wang <xiao.w.wang@intel.com>,
Samuel Holland <samuel.holland@sifive.com>,
linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
Yixun Lan <dlan@gentoo.org>, Longbin Li <looong.bin@gmail.com>
Subject: Re: [PATCH v2 2/3] riscv: add ISA extension parsing for bfloat16 ISA extension
Date: Mon, 4 Nov 2024 12:07:49 +0000 [thread overview]
Message-ID: <20241104-number-recall-85e044c9b72d@spud> (raw)
In-Reply-To: <2e775421-0c3e-48ef-8a8c-6734f7fcf298@rivosinc.com>
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On Mon, Nov 04, 2024 at 10:15:56AM +0100, Clément Léger wrote:
>
>
> On 03/11/2024 08:49, Inochi Amaoto wrote:
> > Add parsing for Zfbmin, Zvfbfmin, Zvfbfwma ISA extension which
> > were ratified in 4dc23d62 ("Added Chapter title to BF16") of
> > the riscv-isa-manual.
> >
> > Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
> > ---
> > arch/riscv/include/asm/hwcap.h | 3 +++
> > arch/riscv/kernel/cpufeature.c | 3 +++
> > 2 files changed, 6 insertions(+)
> >
> > diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
> > index 46d9de54179e..97657fb63af6 100644
> > --- a/arch/riscv/include/asm/hwcap.h
> > +++ b/arch/riscv/include/asm/hwcap.h
> > @@ -93,6 +93,9 @@
> > #define RISCV_ISA_EXT_ZCMOP 84
> > #define RISCV_ISA_EXT_ZAWRS 85
> > #define RISCV_ISA_EXT_SVVPTC 86
> > +#define RISCV_ISA_EXT_ZFBFMIN 87
> > +#define RISCV_ISA_EXT_ZVFBFMIN 88
> > +#define RISCV_ISA_EXT_ZVFBFWMA 89
> >
> > #define RISCV_ISA_EXT_XLINUXENVCFG 127
> >
> > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> > index 3a8eeaa9310c..1b286f5bc591 100644
> > --- a/arch/riscv/kernel/cpufeature.c
> > +++ b/arch/riscv/kernel/cpufeature.c
> > @@ -325,6 +325,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
> > __RISCV_ISA_EXT_DATA(zacas, RISCV_ISA_EXT_ZACAS),
> > __RISCV_ISA_EXT_DATA(zawrs, RISCV_ISA_EXT_ZAWRS),
> > __RISCV_ISA_EXT_DATA(zfa, RISCV_ISA_EXT_ZFA),
> > + __RISCV_ISA_EXT_DATA(zfbfmin, RISCV_ISA_EXT_ZFBFMIN),
> > __RISCV_ISA_EXT_DATA(zfh, RISCV_ISA_EXT_ZFH),
> > __RISCV_ISA_EXT_DATA(zfhmin, RISCV_ISA_EXT_ZFHMIN),
> > __RISCV_ISA_EXT_DATA(zca, RISCV_ISA_EXT_ZCA),
> > @@ -357,6 +358,8 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
> > __RISCV_ISA_EXT_SUPERSET(zve64d, RISCV_ISA_EXT_ZVE64D, riscv_zve64d_exts),
> > __RISCV_ISA_EXT_SUPERSET(zve64f, RISCV_ISA_EXT_ZVE64F, riscv_zve64f_exts),
> > __RISCV_ISA_EXT_SUPERSET(zve64x, RISCV_ISA_EXT_ZVE64X, riscv_zve64x_exts),
> > + __RISCV_ISA_EXT_DATA(zvfbfmin, RISCV_ISA_EXT_ZVFBFMIN),
> > + __RISCV_ISA_EXT_DATA(zvfbfwma, RISCV_ISA_EXT_ZVFBFWMA),
>
> @Conor,
>
> Should we wait for your V/F validation support to be merged before this
> one ?
Uh, I don't really see a reason to hold this up on my account. I can
easily rebase on top when I get the motivation to do more work on that
series.
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next prev parent reply other threads:[~2024-11-04 12:07 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-11-03 7:49 [PATCH v2 0/3] riscv: Add bfloat16 instruction support Inochi Amaoto
2024-11-03 7:49 ` [PATCH v2 1/3] dt-bindings: riscv: add bfloat16 ISA extension description Inochi Amaoto
2024-11-04 12:08 ` Conor Dooley
2024-11-03 7:49 ` [PATCH v2 2/3] riscv: add ISA extension parsing for bfloat16 ISA extension Inochi Amaoto
2024-11-04 9:15 ` Clément Léger
2024-11-04 12:07 ` Conor Dooley [this message]
2024-11-03 7:49 ` [PATCH v2 3/3] riscv: hwprobe: export " Inochi Amaoto
2024-11-04 12:11 ` Clément Léger
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