From: Bjorn Helgaas <helgaas@kernel.org>
To: Lorenzo Bianconi <lorenzo@kernel.org>
Cc: linux-pci@vger.kernel.org, ryder.lee@mediatek.com,
jianjun.wang@mediatek.com, lpieralisi@kernel.org, kw@linux.com,
robh@kernel.org, bhelgaas@google.com,
linux-mediatek@lists.infradead.org, lorenzo.bianconi83@gmail.com,
linux-arm-kernel@lists.infradead.org,
krzysztof.kozlowski+dt@linaro.org, devicetree@vger.kernel.org,
nbd@nbd.name, dd@embedd.com, upstream@airoha.com,
angelogioacchino.delregno@collabora.com,
Jim Quinlan <james.quinlan@broadcom.com>,
Krishna Chaitanya Chundru <quic_krichai@quicinc.com>,
Vidya Sagar <vidyas@nvidia.com>,
Shashank Babu Chinta Venkata <quic_schintav@quicinc.com>
Subject: Re: [PATCH v4 4/4] PCI: mediatek-gen3: Add Airoha EN7581 support
Date: Tue, 5 Nov 2024 15:33:39 -0600 [thread overview]
Message-ID: <20241105213339.GA1487624@bhelgaas> (raw)
In-Reply-To: <aca00bd672ee576ad96d279414fc0835ff31f637.1720022580.git.lorenzo@kernel.org>
[+cc Jim, Krishna, Vidya, Shashank]
On Wed, Jul 03, 2024 at 06:12:44PM +0200, Lorenzo Bianconi wrote:
> Introduce support for Airoha EN7581 PCIe controller to mediatek-gen3
> PCIe controller driver.
> +++ b/drivers/pci/controller/pcie-mediatek-gen3.c
> +#define PCIE_EQ_PRESET_01_REG 0x100
> +#define PCIE_VAL_LN0_DOWNSTREAM GENMASK(6, 0)
> +#define PCIE_VAL_LN0_UPSTREAM GENMASK(14, 8)
> +#define PCIE_VAL_LN1_DOWNSTREAM GENMASK(22, 16)
> +#define PCIE_VAL_LN1_UPSTREAM GENMASK(30, 24)
> ...
> +static int mtk_pcie_en7581_power_up(struct mtk_gen3_pcie *pcie)
> +{
> ...
> + val = FIELD_PREP(PCIE_VAL_LN0_DOWNSTREAM, 0x47) |
> + FIELD_PREP(PCIE_VAL_LN1_DOWNSTREAM, 0x47) |
> + FIELD_PREP(PCIE_VAL_LN0_UPSTREAM, 0x41) |
> + FIELD_PREP(PCIE_VAL_LN1_UPSTREAM, 0x41);
> + writel_relaxed(val, pcie->base + PCIE_EQ_PRESET_01_REG);
This looks like it might be for the Lane Equalization Control
registers (PCIe r6.0, sec 7.7.3.4)?
I would expect those values (0x47, 0x41) to be related to the platform
design, so maybe not completely determined by the SoC itself? Jim and
Krishna have been working on DT schema for the equalization values,
which seems like the right place for them:
https://lore.kernel.org/linux-pci/20241018182247.41130-2-james.quinlan@broadcom.com/
https://lore.kernel.org/r/77d3a1a9-c22d-0fd3-5942-91b9a3d74a43@quicinc.com
Maybe that would be applicable here as well? It would at least be
nice to use a common #define for the Lane Equalization Control
register offset from the capability base.
Although I see that no such #define exists in pci_regs.h, so I guess
there's nothing to do here yet.
The only users of equalization settings I could find so far are:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/pci/controller/dwc/pcie-tegra194.c?id=v6.11#n832
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/pci/controller/dwc/pcie-qcom-common.c?id=v6.12-rc1#n11
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/pci/controller/pcie-mediatek-gen3.c?id=v6.12-rc1#n909
Bjorn
next prev parent reply other threads:[~2024-11-05 21:33 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-07-03 16:12 [PATCH v4 0/4] Add Airoha EN7581 PCIe support Lorenzo Bianconi
2024-07-03 16:12 ` [PATCH v4 1/4] dt-bindings: PCI: mediatek-gen3: add support for Airoha EN7581 Lorenzo Bianconi
2024-07-04 8:23 ` AngeloGioacchino Del Regno
2024-07-10 6:22 ` Jianjun Wang (王建军)
2024-07-03 16:12 ` [PATCH v4 2/4] PCI: mediatek-gen3: Add mtk_gen3_pcie_pdata data structure Lorenzo Bianconi
2024-07-10 6:26 ` Jianjun Wang (王建军)
2024-07-03 16:12 ` [PATCH v4 3/4] PCI: mediatek-gen3: Rely on reset_bulk APIs for PHY reset lines Lorenzo Bianconi
2024-07-10 6:41 ` Jianjun Wang (王建军)
2024-07-03 16:12 ` [PATCH v4 4/4] PCI: mediatek-gen3: Add Airoha EN7581 support Lorenzo Bianconi
2024-07-10 7:02 ` Jianjun Wang (王建军)
2024-11-05 21:33 ` Bjorn Helgaas [this message]
2024-11-06 23:00 ` Jim Quinlan
2024-11-06 23:40 ` Bjorn Helgaas
2024-11-06 20:32 ` Bjorn Helgaas
2024-11-06 22:40 ` Lorenzo Bianconi
2024-11-06 23:31 ` Bjorn Helgaas
2024-11-07 7:39 ` Lorenzo Bianconi
2024-11-07 15:17 ` Bjorn Helgaas
2024-11-07 16:21 ` Lorenzo Bianconi
2024-11-07 16:46 ` Bjorn Helgaas
2024-11-07 21:56 ` Lorenzo Bianconi
2024-11-08 1:23 ` 回复: " Hui Ma (马慧)
2024-11-08 16:33 ` Bjorn Helgaas
2024-11-09 9:40 ` Lorenzo Bianconi
2024-11-11 2:16 ` 回复: " Hui Ma (马慧)
2024-08-20 8:46 ` [PATCH v4 0/4] Add Airoha EN7581 PCIe support Lorenzo Bianconi
2024-08-20 14:01 ` Bjorn Helgaas
2024-09-03 13:47 ` Krzysztof Wilczyński
2024-09-03 13:45 ` Krzysztof Wilczyński
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20241105213339.GA1487624@bhelgaas \
--to=helgaas@kernel.org \
--cc=angelogioacchino.delregno@collabora.com \
--cc=bhelgaas@google.com \
--cc=dd@embedd.com \
--cc=devicetree@vger.kernel.org \
--cc=james.quinlan@broadcom.com \
--cc=jianjun.wang@mediatek.com \
--cc=krzysztof.kozlowski+dt@linaro.org \
--cc=kw@linux.com \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-mediatek@lists.infradead.org \
--cc=linux-pci@vger.kernel.org \
--cc=lorenzo.bianconi83@gmail.com \
--cc=lorenzo@kernel.org \
--cc=lpieralisi@kernel.org \
--cc=nbd@nbd.name \
--cc=quic_krichai@quicinc.com \
--cc=quic_schintav@quicinc.com \
--cc=robh@kernel.org \
--cc=ryder.lee@mediatek.com \
--cc=upstream@airoha.com \
--cc=vidyas@nvidia.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).